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Table of Contents
Preface; Contents; 1: A New Era of Old Electronics; 1.1 Introduction; 1.2 The Call for Energy-Efficiency; 1.3 Energy-Efficiency Limitations of CMOS; 1.3.1 CMOS Scaling; 1.3.2 Minimizing CMOS Energy Consumption; 1.3.3 Temporarily Averting the CMOS Power Crisis; 1.4 Micro-relays as an Energy-Efficient Technology; 1.4.1 Electromechanical Devices; 1.4.2 Energy Outlook for Micro-relays; 1.5 Book Summary; References; 2: Design and Modeling of Micro-relay; 2.1 Introduction; 2.2 Relay Structure and Operation; 2.3 Design and Modeling of Mechanical Beams; 2.3.1 Mechanical Modeling of Cantilever Beams
2.3.2 Mechanical Modeling of Fixed-fixed Beams2.3.3 Impact of Stress Gradient and Residual Stress; 2.3.3.1 Impact on Cantilever Beams; 2.3.3.2 Impact of Residual Stress on Fixed-Fixed Beams; 2.3.4 Stress/Strain Gradient Free Beam Design; 2.4 Design and Modeling of Torsional Beam; 2.5 Dimple Support Design; 2.6 Contact Resistance; 2.7 Dynamic Behavior of Micro-relays; 2.7.1 Effective Mass Model; 2.7.2 Damping Physics; 2.8 Relay Energy Consumption per Operation; Appendix: Spring Constant of a Pinned-Pinned Beam; References; 3: Micro-relay Technologies; 3.1 Introduction
3.2 Process Integration Considerations for Micro-relay Technology3.3 Berkeley Folded-Flexure Relay with Poly-Si0.4Ges Structure and Tungsten Contacts; 3.3.1 Static Performance; 3.3.2 Dynamic Performance; 3.4 KAIST Titanium-Nitride Relay Technology; 3.5 Stanford Laterally Actuated Platinum-Coated Polysilicon Relay; 3.6 Sandia National Laboratories Laterally Actuated Ruthenium Relay; 3.7 Integrations with CMOS; 3.8 University of Pennsylvania Piezoelectric Aluminum Nitride Micro-relay; Conclusion; References; 4: Micro-relay Reliability; 4.1 Introduction; 4.2 Structural Fatigue
4.3 Dielectric Charging4.4 Contact Surface Oxidation; 4.5 Contact Welding; 4.5.1 Contact Endurance Model; 4.5.2 Validation of the Contact Endurance Model; 4.5.3 Design Implications; 4.5.3.1 General Digital Logic Application; 4.5.3.2 CMOS Power Gating Application; Conclusion; References; 5: Optimization and Scaling of Micro-relays for Ultralow-Power Digital Logic; 5.1 Introduction; 5.2 Relay Energy-Delay Optimization; 5.2.1 Sensitivity Analysis; 5.2.2 Sensitivity to Supply Voltage (Vdd); 5.2.3 Sensitivity to Actuation Area (A); 5.2.4 Sensitivity to As-Fabricated Gap Thickness (g)
5.2.5 Sensitivity to Beam Length (L)5.3 Relay Design Optimization; 5.3.1 Optimal Gap Thickness Ratio (gd/g); 5.3.2 Optimal Vdd/Vpi; 5.3.3 Optimal Actuation Area (A) and Supply Voltage (Vdd); 5.3.4 Optimal Beam Length (L); 5.3.5 Relay Design Optimization Procedure; 5.3.6 Energy-Efficiency Limit; 5.4 Scaling Implications; Conclusion; References; 6: Integrated Circuit Design with Micro-relays; 6.1 Introduction; 6.2 Micro-relay Switching Characteristics; 6.2.1 DC Switching Characteristics of Micro-relays; 6.2.2 Dynamic Switching Characteristics of Micro-relays
2.3.2 Mechanical Modeling of Fixed-fixed Beams2.3.3 Impact of Stress Gradient and Residual Stress; 2.3.3.1 Impact on Cantilever Beams; 2.3.3.2 Impact of Residual Stress on Fixed-Fixed Beams; 2.3.4 Stress/Strain Gradient Free Beam Design; 2.4 Design and Modeling of Torsional Beam; 2.5 Dimple Support Design; 2.6 Contact Resistance; 2.7 Dynamic Behavior of Micro-relays; 2.7.1 Effective Mass Model; 2.7.2 Damping Physics; 2.8 Relay Energy Consumption per Operation; Appendix: Spring Constant of a Pinned-Pinned Beam; References; 3: Micro-relay Technologies; 3.1 Introduction
3.2 Process Integration Considerations for Micro-relay Technology3.3 Berkeley Folded-Flexure Relay with Poly-Si0.4Ges Structure and Tungsten Contacts; 3.3.1 Static Performance; 3.3.2 Dynamic Performance; 3.4 KAIST Titanium-Nitride Relay Technology; 3.5 Stanford Laterally Actuated Platinum-Coated Polysilicon Relay; 3.6 Sandia National Laboratories Laterally Actuated Ruthenium Relay; 3.7 Integrations with CMOS; 3.8 University of Pennsylvania Piezoelectric Aluminum Nitride Micro-relay; Conclusion; References; 4: Micro-relay Reliability; 4.1 Introduction; 4.2 Structural Fatigue
4.3 Dielectric Charging4.4 Contact Surface Oxidation; 4.5 Contact Welding; 4.5.1 Contact Endurance Model; 4.5.2 Validation of the Contact Endurance Model; 4.5.3 Design Implications; 4.5.3.1 General Digital Logic Application; 4.5.3.2 CMOS Power Gating Application; Conclusion; References; 5: Optimization and Scaling of Micro-relays for Ultralow-Power Digital Logic; 5.1 Introduction; 5.2 Relay Energy-Delay Optimization; 5.2.1 Sensitivity Analysis; 5.2.2 Sensitivity to Supply Voltage (Vdd); 5.2.3 Sensitivity to Actuation Area (A); 5.2.4 Sensitivity to As-Fabricated Gap Thickness (g)
5.2.5 Sensitivity to Beam Length (L)5.3 Relay Design Optimization; 5.3.1 Optimal Gap Thickness Ratio (gd/g); 5.3.2 Optimal Vdd/Vpi; 5.3.3 Optimal Actuation Area (A) and Supply Voltage (Vdd); 5.3.4 Optimal Beam Length (L); 5.3.5 Relay Design Optimization Procedure; 5.3.6 Energy-Efficiency Limit; 5.4 Scaling Implications; Conclusion; References; 6: Integrated Circuit Design with Micro-relays; 6.1 Introduction; 6.2 Micro-relay Switching Characteristics; 6.2.1 DC Switching Characteristics of Micro-relays; 6.2.2 Dynamic Switching Characteristics of Micro-relays