Foreword; Contents; 1 User Needs; References; 2 Challenges and Limitations for Very High Throughput Decoder Architectures for Soft-Decoding; 2.1 Motivation; 2.2 Architectures for Soft Decision Reed-Solomon Decoders; 2.2.1 Introduction; 2.2.2 Information Set Decoding; 2.2.2.1 Original OSD; 2.2.2.2 Reduced Complexity Algorithm for Hardware; 2.2.2.3 HDD Aided Decoding; 2.2.2.4 Implemented OSD Version; 2.2.3 Hardware Architecture; 2.2.3.1 Architecture Overview; 2.2.3.2 Sorting Unit; 2.2.3.3 Syndrome Calculation Unit; 2.2.3.4 Column Generator Unit; 2.2.3.5 Gaussian Elimination Unit

2.2.3.6 Correction Unit2.2.3.7 Hard Decision Decoder; 2.2.3.8 Fixed Point Quantization Issues; 2.2.3.9 Pipelining and Latency Issues; 2.2.4 Implementation Results; 2.3 Architectures for Turbo Code Decoders; 2.4 High Throughput Architectures for Low Density Parity Check Decoders; 2.4.1 LDPC Decoding; 2.4.2 LDPC Decoder Design Space; 2.4.3 Exploring a New Dimension in the High Throughput LDPC Decoder Design Space; 2.4.3.1 Core Duplication; 2.4.3.2 Unrolling Iterations; 2.4.4 Comparison of Unrolled LDPC Decoders to State-of-the-Art Architectures; 2.4.5 Future Work; References

3 Implementation of Polar Decoders3.1 Introduction to Polar Codes; 3.1.1 Code Construction; 3.1.2 Successive-Cancellation Decoding; 3.1.3 Belief-Propagation Decoding; 3.2 The Successive-Cancellation Decoder Implementation; 3.2.1 Processing Elements; 3.2.2 Partial-Sum Update Logic; 3.2.3 Memory; 3.2.4 Implementation Results; 3.3 The Belief-Propagation Decoder Implementation; 3.4 Simplified Successive-Cancellation Decoding; 3.4.1 Two-Phase Successive-Cancellation Decoding; 3.5 Fast-SSC Decoding; 3.5.1 Node Mergers; 3.5.2 Overall Decoder Architecture; 3.5.3 Processing Unit Architecture

3.5.4 Implementation Results3.6 Implementation Comparison; References; 4 Parallel Architectures for Turbo Product Codes Decoding; 4.1 Introduction; 4.2 TPC Coding and Decoding Principles; 4.2.1 Product Codes; 4.2.2 Iterative Decoding of Product Codes; 4.3 Straightforward Hardware Implementation of a TPC Decoder; 4.3.1 Global TPC Decoder Architecture; 4.3.2 Sequential SISO Decoder Architecture; 4.4 From Parallelism Levels to Parallel Architectures; 4.4.1 Frame Parallelism; 4.4.2 Iteration Parallelism; 4.4.3 Sub-block Parallelism; 4.4.3.1 Barrel Shifter; 4.4.3.2 Omega Network

4.4.4 Symbol Parallelism4.4.4.1 Memory Merging; 4.4.4.2 Fully Parallel SISO Decoder; 4.4.5 Intra-symbol Parallelism; 4.4.6 Comparison of Parallelism Levels; 4.5 TPC Decoder Architecture Based on Symbol Parallelism; 4.5.1 Proposed IM-Free Architecture Using Fully Parallel SISO Decoder; 4.5.2 Toward a Maximal Parallelism Rate; 4.6 Architecture of a Fully Parallel Combinational SISO Decoder; 4.6.1 Algorithmic Parameter Reduction; 4.6.2 Fully Parallel SISO Decoder Architecture; 4.6.2.1 Reception Stage; 4.6.2.2 Test Pattern Processing Stage; 4.6.2.3 Soft-Output Computation Stage