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Table of Contents
Preface; Contents; About the Authors; 1 Introduction; 1.1 Preliminary Background; 1.2 Motivation; 1.3 Book Outline; 2 Design Challenges in Subthreshold Interconnect Circuits; 2.1 Interconnects for VLSI Applications
A Review; 2.1.1 Parasitic Impedance Parameters; 2.1.2 Interconnect Delay; 2.1.3 CMOS Buffer; 2.2 Coupling Capacitance Noise; 2.3 Power Dissipation; 2.4 Weak Inversion for Ultra-Low-Power Logic; 2.5 Variability in Subthreshold Design; 2.5.1 Process Variations; 2.5.2 Temperature Variations; 2.6 Concluding Remarks; 3 Subthreshold Interconnect Circuit Design
3.1 Circuit Model of CMOS Buffer3.2 Analysis of Buffer-Driven Interconnect for Rising Ramp Input; 3.2.1 Fast Ramp; 3.2.2 Determination of tau nsat; 3.2.3 High-to-Low Propagation Delay of a Fast Ramp Signal; 3.2.4 High-to-Low Propagation Delay of a Slow Ramp Signal; 3.2.5 Power Estimation; 3.3 Analysis for Falling Ramp Input; 3.3.1 Fast Ramp; 3.3.2 Determination of tau psat; 3.3.3 Low-to-High Propagation Delay of a Fast Ramp Signal; 3.3.4 Low-to-High Propagation Delay of a Slow Ramp Signal; 3.3.5 Resistive Power Dissipation; 3.4 Comparison with Simulation Results; 3.4.1 Performance Metrics
3.5 Concluding Remarks4 Characterization of Dynamic Crosstalk Effect in Subthreshold Interconnects; 4.1 The Output Voltage of Each CMOS Inverter; 4.2 In-Phase Switching; 4.2.1 Propagation Delay for Fast Ramp; 4.2.2 Propagation Delay for Slow Ramp; 4.3 Out-of-Phase Switching; 4.3.1 Propagation Delay for Fast Ramp; 4.4 Comparison with Simulation Results; 4.5 Concluding Remarks; 5 Subthreshold Interconnect Noise Analysis; 5.1 Inv1 Input Switching from Low-to-High and Inv2 Static High; 5.1.1 Step Input Approximation; 5.1.2 Neglecting Current Through MN2
5.2 Inv1 Input Switching from Low-to-High and Inv2 Static Low5.2.1 Step Input Approximation; 5.3 Design Guidelines for Crosstalk Avoidance; 5.3.1 Power-Delay-Crosstalk-Product: Performance Criterion; 5.4 Concluding Remarks; 6 Variability in Subthreshold Interconnects; 6.1 Process Variability; 6.1.1 Device Variations; 6.1.2 Interconnect Variations; 6.1.3 Dynamic Variations; 6.2 Variability Analysis; 6.2.1 Parametric Analysis; 6.2.2 Process Corner Analysis; 6.2.3 Monte Carlo Analysis; 6.3 Effect of Temperature; 6.3.1 Delay Variation with Temperature; 6.4 Concluding Remarks; Bibliography
A Review; 2.1.1 Parasitic Impedance Parameters; 2.1.2 Interconnect Delay; 2.1.3 CMOS Buffer; 2.2 Coupling Capacitance Noise; 2.3 Power Dissipation; 2.4 Weak Inversion for Ultra-Low-Power Logic; 2.5 Variability in Subthreshold Design; 2.5.1 Process Variations; 2.5.2 Temperature Variations; 2.6 Concluding Remarks; 3 Subthreshold Interconnect Circuit Design
3.1 Circuit Model of CMOS Buffer3.2 Analysis of Buffer-Driven Interconnect for Rising Ramp Input; 3.2.1 Fast Ramp; 3.2.2 Determination of tau nsat; 3.2.3 High-to-Low Propagation Delay of a Fast Ramp Signal; 3.2.4 High-to-Low Propagation Delay of a Slow Ramp Signal; 3.2.5 Power Estimation; 3.3 Analysis for Falling Ramp Input; 3.3.1 Fast Ramp; 3.3.2 Determination of tau psat; 3.3.3 Low-to-High Propagation Delay of a Fast Ramp Signal; 3.3.4 Low-to-High Propagation Delay of a Slow Ramp Signal; 3.3.5 Resistive Power Dissipation; 3.4 Comparison with Simulation Results; 3.4.1 Performance Metrics
3.5 Concluding Remarks4 Characterization of Dynamic Crosstalk Effect in Subthreshold Interconnects; 4.1 The Output Voltage of Each CMOS Inverter; 4.2 In-Phase Switching; 4.2.1 Propagation Delay for Fast Ramp; 4.2.2 Propagation Delay for Slow Ramp; 4.3 Out-of-Phase Switching; 4.3.1 Propagation Delay for Fast Ramp; 4.4 Comparison with Simulation Results; 4.5 Concluding Remarks; 5 Subthreshold Interconnect Noise Analysis; 5.1 Inv1 Input Switching from Low-to-High and Inv2 Static High; 5.1.1 Step Input Approximation; 5.1.2 Neglecting Current Through MN2
5.2 Inv1 Input Switching from Low-to-High and Inv2 Static Low5.2.1 Step Input Approximation; 5.3 Design Guidelines for Crosstalk Avoidance; 5.3.1 Power-Delay-Crosstalk-Product: Performance Criterion; 5.4 Concluding Remarks; 6 Variability in Subthreshold Interconnects; 6.1 Process Variability; 6.1.1 Device Variations; 6.1.2 Interconnect Variations; 6.1.3 Dynamic Variations; 6.2 Variability Analysis; 6.2.1 Parametric Analysis; 6.2.2 Process Corner Analysis; 6.2.3 Monte Carlo Analysis; 6.3 Effect of Temperature; 6.3.1 Delay Variation with Temperature; 6.4 Concluding Remarks; Bibliography