Low power interconnect design [electronic resource] / Sandeep Saini.

Unlimited

Authorized users

Can lend chapters, not whole ebooks

Low power interconnect design [electronic resource] / Sandeep Saini.

9781461413233 electronic book
1461413230 electronic book
9781461413226

New York, NY : Springer, 2015.

English

1 online resource (xvii, 152 pages) : illustrations.

10.1007/978-1-4614-1323-3 doi

TK7874.53

621.3815

This book provides practical solutions for delay and power reduction for on-chip interconnects and buses. It provides an in depth description of the problem of signal delay and extra power consumption, possible solutions for delay and glitch removal, while considering the power reduction of the total system. Coverage focuses on use of the Schmitt Trigger as an alternative approach to buffer insertion for delay and power reduction in VLSI interconnects. In the last section of the book, various bus coding techniques are discussed to minimize delay and power in address and data buses. · Provides practical solutions for delay and power reduction for on-chip interconnects and buses; · Focuses on Deep Sub micron technology devices and interconnects; · Offers in depth analysis of delay, including details regarding crosstalk and parasitics; · Describes use of the Schmitt Trigger as a versatile alternative approach to buffer insertion for delay and power reduction in VLSI interconnects; · Provides detailed simulation results to support the theoretical discussions. · Provides details of delay and power efficient bus coding techniques.

Includes bibliographical references.

Access limited to authorized users.

Online resource; title from PDF title page (SpringerLink, viewed June 15, 2015).

Online Resources > Ebooks
All Resources