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000727694 020__ $$a9781461413233$$qelectronic book
000727694 020__ $$a1461413230$$qelectronic book
000727694 020__ $$z9781461413226
000727694 0247_ $$a10.1007/978-1-4614-1323-3$$2doi
000727694 035__ $$aSP(OCoLC)ocn911037553
000727694 035__ $$aSP(OCoLC)911037553
000727694 040__ $$aGW5XE$$beng$$erda$$epn$$cGW5XE$$dN$T$$dIDEBK$$dCDX$$dYDXCP$$dEBLCP$$dDEBSZ$$dUPM$$dAZU
000727694 049__ $$aISEA
000727694 050_4 $$aTK7874.53
000727694 08204 $$a621.3815$$223
000727694 1001_ $$aSaini, Sandeep,$$eauthor.
000727694 24510 $$aLow power interconnect design$$h[electronic resource] /$$cSandeep Saini.
000727694 264_1 $$aNew York, NY :$$bSpringer,$$c2015.
000727694 300__ $$a1 online resource (xvii, 152 pages) :$$billustrations.
000727694 336__ $$atext$$btxt$$2rdacontent
000727694 337__ $$acomputer$$bc$$2rdamedia
000727694 338__ $$aonline resource$$bcr$$2rdacarrier
000727694 504__ $$aIncludes bibliographical references.
000727694 5050_ $$aPart I Basics of Interconnect Design -- Introduction to Interconnects -- CMOS Buffer -- Part II Buffer and Schmidt trigger Insertion Techniques for Low Power Interconnect Design -- Buffer Insertion as a Solution to Interconnect Issues -- Schmidt Trigger Approach -- Part III Bus Coding Techniques for Low Power Interconnect Design -- Bus Coding Techniques.
000727694 506__ $$aAccess limited to authorized users.
000727694 520__ $$aThis book provides practical solutions for delay and power reduction for on-chip interconnects and buses. It provides an in depth description of the problem of signal delay and extra power consumption, possible solutions for delay and glitch removal, while considering the power reduction of the total system. Coverage focuses on use of the Schmitt Trigger as an alternative approach to buffer insertion for delay and power reduction in VLSI interconnects. In the last section of the book, various bus coding techniques are discussed to minimize delay and power in address and data buses. · Provides practical solutions for delay and power reduction for on-chip interconnects and buses; · Focuses on Deep Sub micron technology devices and interconnects; · Offers in depth analysis of delay, including details regarding crosstalk and parasitics; · Describes use of the Schmitt Trigger as a versatile alternative approach to buffer insertion for delay and power reduction in VLSI interconnects; · Provides detailed simulation results to support the theoretical discussions. · Provides details of delay and power efficient bus coding techniques.
000727694 588__ $$aOnline resource; title from PDF title page (SpringerLink, viewed June 15, 2015).
000727694 650_0 $$aInterconnects (Integrated circuit technology)$$xDesign.
000727694 852__ $$bebk
000727694 85640 $$3SpringerLink$$uhttps://univsouthin.idm.oclc.org/login?url=http://link.springer.com/10.1007/978-1-4614-1323-3$$zOnline Access$$91397441.1
000727694 909CO $$ooai:library.usi.edu:727694$$pGLOBAL_SET
000727694 980__ $$aEBOOK
000727694 980__ $$aBIB
000727694 982__ $$aEbook
000727694 983__ $$aOnline
000727694 994__ $$a92$$bISE