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Table of Contents
Preface; Contents; Abbreviations; Symbols; 1 Introduction; 1.1 Background; 1.2 What This Book Is About; 1.3 Motivation; 1.4 Major Contributions of This Book; 1.5 Overview of the Book Chapters; 1.6 Overall Message of the Book; References; 2 Fundamentals of Reversible Logic; 2.1 Preliminaries; 2.2 Basic Definitions; 2.3 Reversible Logic Gates; 2.3.1 Feynman Gate; 2.3.2 Toffoli Gate; 2.3.3 Fredkin Gate; 2.4 Reversible Logic Synthesis; 2.5 Overview of Reversible Logic Synthesis Methods; 2.6 The Elimination of Garbage in Binary Reversible Circuits; References
3 Methods of Reversible Logic Synthesis3.1 Reversible Expansions and Reversible Spectral Transforms; 3.1.1 Reversible Ternary Shannon and Davio Expansions; 3.1.2 Reversible Shannon Spectral Transforms; 3.1.3 Reversible Davio Spectral Transforms; 3.2 The Elimination of Garbage in Ternary Reversible Circuits; 3.3 Reversible Decision Trees (RDTs); 3.4 Reversible Decision Diagrams (RDDs); 3.5 Reversible Lattice Circuits; 3.5.1 Symmetric and Non-symmetric Functions; 3.5.2 Two-Dimensional Lattice Circuits; 3.5.3 Three-Dimensional Lattice Circuits
3.5.4 Algorithms for Realizing the Shannon/Davio Expansions of Ternary Functions into 3D Lattice Circuits3.5.4.1 An Algorithm for the Shannon Expansion; 3.5.4.2 An Algorithm for the Davio0 Expansion; 3.5.4.3 New Algorithms for the Shannon/Davio Hybrid Expansions; 3.5.5 Complete Example for the Implementation of Ternary Functions Using 3D Lattice Circuits; 3.5.6 New Minimal Realization Method for 3D Lattice Circuits; 3.5.7 Lattice Circuit Synthesis Using ISID; 3.5.8 The Creation of Reversible Lattice Structures; 3.5.9 3D Ternary Davio Reversible Lattice Structures
3.6 Reversible Fast Transform Circuits3.7 Group-Theoretic Representations; 3.8 Reversible Reconstructability Analysis Circuits; 3.8.1 Ternary MRA; 3.8.2 Reversible MRA (RMRA); 3.9 Reversible Programmable Gate Array (RPGA); 3.9.1 Definitions; 3.9.2 (2 * 2) Net Structures and RPGAs; 3.9.3 The New Reversible Gate (SALEEM); 3.9.4 Novel Design of RPGA Based on the SALEEM Reversible Gate; 3.10 Reversible Cascade Circuits; 3.11 Spectral-Based Synthesis Method; 3.12 Transformation-Based Network Synthesis of Fredkin-Toffoli Cascade Gates; 3.13 Heuristic Algorithm for Reversible Logic Synthesis
3.14 Constructive Synthesis of Reversible Circuits by NOT and (n 2212 1)-CNOT Gates3.15 Summary; References; 4 Evaluation of the Reversible Logic Synthesis Methodologies; 4.1 NPN-Classification of Logic Functions; 4.2 New Evaluation Procedure of Reversible Synthesis Methods; 4.3 Comparison Between the Various Reversible Synthesis Methodologies; 4.4 Summary; References; 5 Reversible Sequential Logic Circuits; 5.1 Reversible Flip Flops; 5.1.1 Reversible RS Flip Flop; 5.1.2 Reversible Clocked RS Flip Flop; 5.1.3 Reversible D Flip Flop; 5.1.4 Reversible JK Flip Flop; 5.1.5 Reversible T Flip Flop
3 Methods of Reversible Logic Synthesis3.1 Reversible Expansions and Reversible Spectral Transforms; 3.1.1 Reversible Ternary Shannon and Davio Expansions; 3.1.2 Reversible Shannon Spectral Transforms; 3.1.3 Reversible Davio Spectral Transforms; 3.2 The Elimination of Garbage in Ternary Reversible Circuits; 3.3 Reversible Decision Trees (RDTs); 3.4 Reversible Decision Diagrams (RDDs); 3.5 Reversible Lattice Circuits; 3.5.1 Symmetric and Non-symmetric Functions; 3.5.2 Two-Dimensional Lattice Circuits; 3.5.3 Three-Dimensional Lattice Circuits
3.5.4 Algorithms for Realizing the Shannon/Davio Expansions of Ternary Functions into 3D Lattice Circuits3.5.4.1 An Algorithm for the Shannon Expansion; 3.5.4.2 An Algorithm for the Davio0 Expansion; 3.5.4.3 New Algorithms for the Shannon/Davio Hybrid Expansions; 3.5.5 Complete Example for the Implementation of Ternary Functions Using 3D Lattice Circuits; 3.5.6 New Minimal Realization Method for 3D Lattice Circuits; 3.5.7 Lattice Circuit Synthesis Using ISID; 3.5.8 The Creation of Reversible Lattice Structures; 3.5.9 3D Ternary Davio Reversible Lattice Structures
3.6 Reversible Fast Transform Circuits3.7 Group-Theoretic Representations; 3.8 Reversible Reconstructability Analysis Circuits; 3.8.1 Ternary MRA; 3.8.2 Reversible MRA (RMRA); 3.9 Reversible Programmable Gate Array (RPGA); 3.9.1 Definitions; 3.9.2 (2 * 2) Net Structures and RPGAs; 3.9.3 The New Reversible Gate (SALEEM); 3.9.4 Novel Design of RPGA Based on the SALEEM Reversible Gate; 3.10 Reversible Cascade Circuits; 3.11 Spectral-Based Synthesis Method; 3.12 Transformation-Based Network Synthesis of Fredkin-Toffoli Cascade Gates; 3.13 Heuristic Algorithm for Reversible Logic Synthesis
3.14 Constructive Synthesis of Reversible Circuits by NOT and (n 2212 1)-CNOT Gates3.15 Summary; References; 4 Evaluation of the Reversible Logic Synthesis Methodologies; 4.1 NPN-Classification of Logic Functions; 4.2 New Evaluation Procedure of Reversible Synthesis Methods; 4.3 Comparison Between the Various Reversible Synthesis Methodologies; 4.4 Summary; References; 5 Reversible Sequential Logic Circuits; 5.1 Reversible Flip Flops; 5.1.1 Reversible RS Flip Flop; 5.1.2 Reversible Clocked RS Flip Flop; 5.1.3 Reversible D Flip Flop; 5.1.4 Reversible JK Flip Flop; 5.1.5 Reversible T Flip Flop