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000752144 019__ $$a931592313$$a932333286
000752144 020__ $$a9783319242026$$q(electronic book)
000752144 020__ $$a3319242024$$q(electronic book)
000752144 020__ $$z9783319242002
000752144 0247_ $$a10.1007/978-3-319-24202-6$$2doi
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000752144 050_4 $$aTK7868.L6
000752144 08204 $$a621.39/5$$223
000752144 1001_ $$aBarkalov, Alexander,$$eauthor.
000752144 24510 $$aLogic synthesis for FPGA-based finite state machines$$h[electronic resource] /$$cAlexander Barkalov, Larysa Titarenko, Malgorzata Kolopienczyk, Kamil Mielcarek and Grzegorz Bazydlo.
000752144 264_1 $$aCham :$$bSpringer,$$c2016.
000752144 264_4 $$c©2016
000752144 300__ $$a1 online resource.
000752144 336__ $$atext$$btxt$$2rdacontent
000752144 337__ $$acomputer$$bc$$2rdamedia
000752144 338__ $$aonline resource$$bcr$$2rdacarrier
000752144 4901_ $$aStudies in systems, decision and control ;$$vvolume 38
000752144 504__ $$aIncludes bibliographical references and index.
000752144 5050_ $$aPreface; Contents; Abbreviations; 1 Background of Finite State Machines and Programmable Logic; 1.1 Basic Models of FSMs; 1.2 Logic Synthesis for Microprogram Automata; 1.3 Logic Synthesis for Microprogram Control Units; 1.4 Logic Synthesis for Compositional MCUs; 1.5 Hardware Reduction for FPLD-Based FSMs; References; 2 Field Programmable Gate Arrays in FSM Design; 2.1 General Characteristic of FPGAs; 2.2 Trivial Implementing FPGA-Based FSMs; 2.3 Methods of State Assignment; 2.4 Hardware Reduction for FPGA-Based FSMs; References; 3 Object Codes Transformation for Mealy FSMs
000752144 5058_ $$a3.1 Principle of OCT for Mealy FSMs3.2 Synthesis of FPGA-Based Mealy FSMs with Transformation of States; 3.3 Synthesis of FPGA-Based Mealy FSMs with Transformation of CMOs; 3.4 Replacement of Logical Conditions in Mealy FSMs with OCT; 3.5 Analysis of Proposed Methods; References; 4 Object Codes Transformation for Moore FSMs ; 4.1 Principle of OCT for Moore FSMs; 4.2 Synthesis of FPGA-Based Moore FSMs with Transformations of States; 4.3 Synthesis of FPGA-Based Moore FSMs with Transformation of CMOs; 4.4 Replacement of Logical Conditions in Moore FSMs with OCT; References
000752144 5058_ $$a5 Distribution of Class Codes in Moore FSMs5.1 The Case of CPLD-Based FSMs; 5.2 Two Sources of Class Codes in FPGA-Based Moore FSMs; 5.3 Three Sources of Class Codes in FPGA-Based Moore FSMs; 5.4 Replacement of Logical Conditions and Distribution of Class Codes; 5.5 Increasing the Number of Class Variables; References; 6 Hardware Reduction in Multidirectional Moore FSMs; 6.1 Hardware Reduction in Two-Directional Moore FSMs; 6.2 Hardware Reduction in 3-Directional Moore FSMs; 6.3 Replacement of Logical Conditions for K-Directional Moore FSMs; References; 7 Design of EMB-Based Mealy FSMs
000752144 5058_ $$a7.1 Trivial Implementing Mealy FSMs7.2 Encoding of Objects in Mealy FSMs; 7.3 Replacement of Logical Conditions for Mealy FSMs; 7.4 Hardware Reduction for BRLC; References; 8 Design of EMB-Based Moore FSMs; 8.1 Trivial Implementing Moore FSMs; 8.2 Structural Decomposition for Moore FSMs; 8.3 Optimization of BIMF Based on Pseudoequivalent States; 8.4 Optimizing LUTer in Replacement of Logical Conditions; References; Conclusion; Index
000752144 506__ $$aAccess limited to authorized users.
000752144 520__ $$aThis book discusses control units represented by the model of a finite state machine (FSM). It contains various original methods and takes into account the peculiarities of field-programmable gate arrays (FPGA) chips and a FSM model. It shows that one of the peculiarities of FPGA chips is the existence of embedded memory blocks (EMB). The book is devoted to the solution of problems of logic synthesis and reduction of hardware amount in control units. The book will be interesting and useful for researchers and PhD students in the area of Electrical Engineering and Computer Science, as well as for designers of modern digital systems.
000752144 588__ $$aOnline resource; title from PDF title page (viewed October 20,  2015).
000752144 650_0 $$aLogic design.
000752144 650_0 $$aField programmable gate arrays.
000752144 7001_ $$aTitarenko, Larysa,$$eauthor.
000752144 7001_ $$aKolopienczyk, Malgorzata,$$eauthor.
000752144 7001_ $$aMielcarek, Kamil,$$eauthor.
000752144 7001_ $$aBazydlo, Grzegorz,$$eauthor.
000752144 77608 $$iPrint version:$$aBarkalov, Alexander$$tLogic Synthesis for FPGA-Based Finite State Machines$$dCham : Springer International Publishing,c2015$$z9783319242002
000752144 830_0 $$aStudies in systems, decision and control ;$$vv. 38.
000752144 852__ $$bebk
000752144 85640 $$3SpringerLink$$uhttps://univsouthin.idm.oclc.org/login?url=http://link.springer.com/10.1007/978-3-319-24202-6$$zOnline Access$$91397441.1
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000752144 980__ $$aBIB
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