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000753997 020__ $$a9783319271774$$q(electronic book)
000753997 020__ $$a3319271776$$q(electronic book)
000753997 020__ $$z9783319271750
000753997 0247_ $$a10.1007/978-3-319-27177-4$$2doi
000753997 035__ $$aSP(OCoLC)ocn941779228
000753997 035__ $$aSP(OCoLC)941779228
000753997 040__ $$aN$T$$beng$$erda$$epn$$cN$T$$dGW5XE$$dYDXCP$$dIDEBK$$dAZU$$dCDX$$dEBLCP$$dN$T$$dOCLCF$$dCOO
000753997 049__ $$aISEA
000753997 050_4 $$aTK7874.85
000753997 08204 $$a621.3815$$223
000753997 1001_ $$aBindal, Ahmet,$$eauthor.
000753997 24510 $$aSilicon nanowire transistors$$h[electronic resource] /$$cAhmet Bindal, Sotoudeh Hamedi-Hagh.
000753997 264_1 $$aCham :$$bSpringer,$$c2016.
000753997 300__ $$a1 online resource (xiv, 165 pages) :$$billustrations.
000753997 336__ $$atext$$btxt$$2rdacontent
000753997 337__ $$acomputer$$bc$$2rdamedia
000753997 338__ $$aonline resource$$bcr$$2rdacarrier
000753997 504__ $$aIncludes bibliographical references and index.
000753997 5050_ $$aDual Work Function Silicon Nanowire MOS Transistors -- Single Work Function Silicon Nanowire MOS Transistors -- Spice Modeling For Analog and Digital Applications -- High-Speed Analog Applications -- Radio Frequency (RF) Applications -- SRAM Mega Cell Design for Digital Applications -- Field-Programmable-Gate-Array (FPGA) -- Integrate-And-Fire Spiking (IFS) Neuron -- Direct Sequence Spread Spectrum (DSSS) Base-Band Transmitter.-.
000753997 506__ $$aAccess limited to authorized users.
000753997 520__ $$aThis book describes the n and p-channel Silicon Nanowire Transistor (SNT) designs with single and dual-work functions, emphasizing low static and dynamic power consumption. The authors describe a process flow for fabrication and generate SPICE models for building various digital and analog circuits. These include an SRAM, a baseband spread spectrum transmitter, a neuron cell and a Field Programmable Gate Array (FPGA) platform in the digital domain, as well as high bandwidth single-stage and operational amplifiers, RF communication circuits in the analog domain, in order to show this technology's true potential for the next generation VLSI. Describes Silicon Nanowire (SNW) Transistors, as vertically constructed MOS n and p-channel transistors, with low static and dynamic power consumption and small layout footprint; Targets System-on-Chip (SoC) design, supporting very high transistor count (ULSI), minimal power consumption requiring inexpensive substrates for packaging; Enables fabrication of different types of memory on the same chip, such as capacitive cells and transistors with floating gates that can be used as DRAMs and Flash memories.
000753997 588__ $$aOnline resource; title from PDF title page (SpringerLink, viewed February 29, 2016).
000753997 650_0 $$aNanowires.
000753997 650_0 $$aNanosilicon.
000753997 650_0 $$aTransistors.
000753997 7001_ $$aHamedi-Hagh, Sotoudeh,$$eauthor.
000753997 77608 $$iPrint version:$$z9783319271750
000753997 852__ $$bebk
000753997 85640 $$3SpringerLink$$uhttps://univsouthin.idm.oclc.org/login?url=http://link.springer.com/10.1007/978-3-319-27177-4$$zOnline Access$$91397441.1
000753997 909CO $$ooai:library.usi.edu:753997$$pGLOBAL_SET
000753997 980__ $$aEBOOK
000753997 980__ $$aBIB
000753997 982__ $$aEbook
000753997 983__ $$aOnline
000753997 994__ $$a92$$bISE