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000778255 019__ $$a974651743$$a981099953
000778255 020__ $$a9783319488998$$q(electronic book)
000778255 020__ $$a3319488996$$q(electronic book)
000778255 020__ $$z9783319488981
000778255 0247_ $$a10.1007/978-3-319-48899-8$$2doi
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000778255 08204 $$a621.39/5$$223
000778255 08204 $$a620
000778255 1001_ $$aPosser, Gracieli,$$eauthor.
000778255 24510 $$aElectromigration inside logic cells :$$bmodeling, analyzing and mitigating signal electromigration in NanoCMOS /$$cGracieli Posser, Sachin S. Sapatnekar, Ricardo Reis.
000778255 264_1 $$aCham, Switzerland :$$bSpringer,$$c2017.
000778255 300__ $$a1 online resource.
000778255 336__ $$atext$$btxt$$2rdacontent
000778255 337__ $$acomputer$$bc$$2rdamedia
000778255 338__ $$aonline resource$$bcr$$2rdacarrier
000778255 347__ $$atext file$$bPDF$$2rda
000778255 504__ $$aIncludes bibliographical references.
000778255 5050_ $$aPreface; Acknowledgments; Contents; List of Figures; List of Tables; Abbreviations; 1 Introduction; 1.1 Reliability and Electromigration; 1.2 Electromigration in Future Technologies; 1.3 Motivation and Contributions; 1.4 Monograph Outline; 2 State of the Art; 2.1 Mitigating the EM Effects in Different IC Design Flow Stages; 2.1.1 Managing Electromigration in Logic Designs; 2.1.2 Electromigration Impact in Future Technologies; 2.1.3 Smart Non-default Routing for Clock Power Reduction; 2.1.4 Impacts of Electromigration Awareness
000778255 5058_ $$a2.2 Mitigating the EM Effects in Different Types of Interconnections2.2.1 TSVs; 2.2.2 Power Delivery Network; 2.2.3 Clock Network; 2.2.4 Vias; 2.2.5 Signal Interconnects; 2.2.6 Cell-Internal EM; 2.2.6.1 Accurate Current Estimation for Interconnect Reliability Analysis (Jain12); 2.2.6.2 CMOS Inverter and Standard Cell the Same(patenteempindomae2001cmos); 2.3 Summary of Related Works; 2.4 Conclusions; 3 Modeling Cell-Internal EM; 3.1 Modeling Time-to-Failure Under EM; 3.2 Joule Heating; 3.2.1 Local Hot Spots from Joule Heating; 3.3 Current Divergence
000778255 5058_ $$a3.3.1 New Electromigration Validation: Via Node Vector Method3.3.2 Applying Current Divergence in the Proposed EM Model; 3.3.3 The Impact of Blech Length on Cell-Internal Interconnects; 3.4 Conclusions; 4 Current Calculation; 4.1 Current Flows Using Graph Traversals; 4.2 Algebra for Average/RMS Current Updates; 4.2.1 Algebra for Computing Average Current; 4.2.2 Algebra for Computing the RMS Current; 4.2.2.1 Example; 4.3 Results; 5 Experimental Setup; 6 Results; 6.1 The Electromigration Effects for Different Logic Gates; 6.1.1 NAND2_X2 and NOR2_X2 Gates
000778255 5058_ $$a6.1.1.1 TTF Improvement by Layout Modifications6.1.2 AOI21_X2; 6.1.2.1 TTF Improvement by Layout Modifications; 6.1.3 NOR2_X4; 6.1.4 INV_X16; 6.2 Conclusion; 7 Analyzing the Electromigration Effects on Different Metal Layers and Different Wire Lengths; 7.1 Experimental Setup; 7.2 Simulation Results; 7.3 Conclusion; 8 Conclusions; 8.1 Future Works; A Impact on Physical Synthesis Considering Different Amounts of Instances with EM Awareness; B Coupling Capacitance Currents; References
000778255 506__ $$aAccess limited to authorized users.
000778255 520__ $$aThis book describes new and effective methodologies for modeling, analyzing and mitigating cell-internal signal electromigration in nanoCMOS, with significant circuit lifetime improvements and no impact on performance, area and power. The authors are the first to analyze and propose a solution for the electromigration effects inside logic cells of a circuit. They show in this book that an interconnect inside a cell can fail reducing considerably the circuit lifetime and they demonstrate a methodology to optimize the lifetime of circuits, by placing the output, Vdd and Vss pin of the cells in the less critical regions, where the electromigration effects are reduced. Readers will be enabled to apply this methodology only for the critical cells in the circuit, avoiding impact in the circuit delay, area and performance, thus increasing the lifetime of the circuit without loss in other characteristics. .
000778255 588__ $$aOnline resource; title from PDF title page (SpringerLink, viewed January 3, 2017).
000778255 650_0 $$aLogic circuits.
000778255 650_0 $$aElectrodiffusion.
000778255 7001_ $$aSapatnekar, Sachin S.,$$d1967-$$eauthor.
000778255 7001_ $$aReis, Ricardo,$$eauthor.
000778255 77608 $$iPrint version:$$z9783319488981
000778255 852__ $$bebk
000778255 85640 $$3SpringerLink$$uhttps://univsouthin.idm.oclc.org/login?url=http://link.springer.com/10.1007/978-3-319-48899-8$$zOnline Access$$91397441.1
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000778255 980__ $$aEBOOK
000778255 980__ $$aBIB
000778255 982__ $$aEbook
000778255 983__ $$aOnline
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