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Part I Architecture and Implementation Perspective; 1 A Perspective on Dark Silicon; The Dark Silicon Phenomenon; Power Density; Power Consumption in CMOS Chips; Slack Voltage Scaling; Leakage Power; Thermal Issues; Challenges and Consequences of Dark Silicon; Performance; Energy Efficiency; Resource Allocation and Utilization; Thermal Management; Solutions for Dark Silicon; Architecture and Implementation Perspective; Run-Time Resource Management: Computational Perspective; Design and Management: Communication Perspective; Summary; References
2 Dark vs. Dim Silicon and Near-Threshold ComputingIntroduction; Related Work; Lumos Framework; Technology Modeling; Frequency Modeling; Core Modeling; Power; Performance; Baseline; Accelerator Modeling; Workload Modeling; System Configuration; Discussions; Lumos Release; Design Space Exploration; Effectiveness of Dim Silicon with Near-Threshold Operation; Dim Silicon with Reconfigurable Logic; Dim Silicon with ASICs; Dim Silicon with Accelerators(RL and ASIC) on General-Purpose Workload; Benefit of ASIC Accelerators; Sensitivity of ASIC Performance Ratio; Alternative Serial Cores
ConclusionsReferences; 3 The SiLago Solution: Architecture and Design Methods for a Heterogeneous Dark Silicon Aware Coarse Grain Reconfigurable Fabric; Introduction; State-of-the-Art Review and Problem Analysis; State-of-the-Art Review of the Techniques to Deal with Dark Silicon Constraints; Problem Analysis; Partial Computation-Centric Customization; Inefficient Software-Centric Implementation Style; Lack of Dynamic Runtime Customization; Large Engineering Cost for Customization; The SiLago Platform; Dynamically Reconfigurable Resource Array; Distributed Memory Architecture
Dynamic Customization of Parallelism and Voltage Frequency ScalingThe Global Interconnect and Reconfiguration Infrastructure in the SiLago Platform; Flexilators and System Controller; Private Execution Partitions: Complete and Dynamic Hardware Centric Custom Implementation for a Predictable and Composable System; Differentiating SiLago Platform with Other Implementation Styles; Automating the Complete Customization; SiLago Physical Design Platform Overview; SiLago Platform Based Design Flow vs. Standard Cell Based Design Flow; The SiLago Design Flow: Automating the Customization
SiLago Physical Design Platform DevelopmentFunction Implementation Library Using AlgoSil High-Level Synthesis; Sub-System/Application-Level Synthesis Using Sylva; Experimental Results; Computational and Silicon Efficiencies of the SiLago Platform; Complete Customization of the SiLago Platform; Dynamic Parallelism and Voltage Frequency Scaling; SiLago Design Methodology; The Overhead Incurred by SiLago's Application-Level Synthesis; The Efficiency of FIMP Library Development; Conclusion and Future Work; References
2 Dark vs. Dim Silicon and Near-Threshold ComputingIntroduction; Related Work; Lumos Framework; Technology Modeling; Frequency Modeling; Core Modeling; Power; Performance; Baseline; Accelerator Modeling; Workload Modeling; System Configuration; Discussions; Lumos Release; Design Space Exploration; Effectiveness of Dim Silicon with Near-Threshold Operation; Dim Silicon with Reconfigurable Logic; Dim Silicon with ASICs; Dim Silicon with Accelerators(RL and ASIC) on General-Purpose Workload; Benefit of ASIC Accelerators; Sensitivity of ASIC Performance Ratio; Alternative Serial Cores
ConclusionsReferences; 3 The SiLago Solution: Architecture and Design Methods for a Heterogeneous Dark Silicon Aware Coarse Grain Reconfigurable Fabric; Introduction; State-of-the-Art Review and Problem Analysis; State-of-the-Art Review of the Techniques to Deal with Dark Silicon Constraints; Problem Analysis; Partial Computation-Centric Customization; Inefficient Software-Centric Implementation Style; Lack of Dynamic Runtime Customization; Large Engineering Cost for Customization; The SiLago Platform; Dynamically Reconfigurable Resource Array; Distributed Memory Architecture
Dynamic Customization of Parallelism and Voltage Frequency ScalingThe Global Interconnect and Reconfiguration Infrastructure in the SiLago Platform; Flexilators and System Controller; Private Execution Partitions: Complete and Dynamic Hardware Centric Custom Implementation for a Predictable and Composable System; Differentiating SiLago Platform with Other Implementation Styles; Automating the Complete Customization; SiLago Physical Design Platform Overview; SiLago Platform Based Design Flow vs. Standard Cell Based Design Flow; The SiLago Design Flow: Automating the Customization
SiLago Physical Design Platform DevelopmentFunction Implementation Library Using AlgoSil High-Level Synthesis; Sub-System/Application-Level Synthesis Using Sylva; Experimental Results; Computational and Silicon Efficiencies of the SiLago Platform; Complete Customization of the SiLago Platform; Dynamic Parallelism and Voltage Frequency Scaling; SiLago Design Methodology; The Overhead Incurred by SiLago's Application-Level Synthesis; The Efficiency of FIMP Library Development; Conclusion and Future Work; References