Preface; Editorial Acknowledgements; Contents; Dr. Vijay Nath; 1 An Autonomous Power and Clock Gating Technique in SRAM-Based FPGA; 1.1 Introduction; 1.2 Power and Clock Gating; 1.2.1 Power Gating; 1.2.2 Clock Gating; 1.3 Transistor-Level Design; 1.3.1 Logic Element; 1.3.2 TILE; 1.4 Proposed Power and Clock Gating Technique; 1.4.1 Method of Gating; 1.4.2 Power and Clock-Gated TILE; 1.5 Results; 1.6 Conclusion; Acknowledgments; Reference; 2 A Hardware Implementation of Evolvable Embedded System for Combinational Logic Circuits Using Virtex 6 FPGA; 2.1 Introduction

2.2 Structure of Evolvable Embedded System2.2.1 Study of VRA; 2.2.2 Genetic Algorithm Flow; 2.2.3 Reconfigurable FPGA Chip; 2.3 Evolvable Embedded System Design; 2.4 Implementation; 2.5 Results; 2.6 Conclusions; References; 3 Evaluation of Wavelet-Based Speech Codecs for VoIP Applications; 3.1 Introduction; 3.2 Various Wavelet Families; 3.3 Speech Signal Processing Using Wavelet Transform; 3.4 Performance Evaluation Parameters; 3.5 Results; 3.6 Conclusions; References; 4 User Demand Wireless Network Selection Using Game Theory; 4.1 Introduction; 4.2 Game Theory and Network Selection

4.3 Proposed Work4.3.1 Energy Utility; 4.3.2 Quality Utility; 4.3.3 Cost Utility; 4.3.4 Ranking Methods; 4.4 Results and Discussions; 4.5 Conclusion and Future Work; References; 5 Leakage Reduction by Test Pattern Reordering; 5.1 Introduction; 5.2 Related Work; 5.3 Proposed Algorithm; 5.3.1 Direct Copy; 5.3.2 Crossover; 5.3.3 Mutation; 5.4 Calculation of Runtime Leakage Power; 5.5 Experimental Result; 5.6 Conclusion; References; 6 Review on Band-Notching Techniques for Ultrawideband Antenna; 6.1 Introduction; 6.2 Design of Band Notch; 6.3 Band-Notching Techniques

6.3.1 Defected Ground Structure (DGS)6.3.2 Slot-Loading Effects; 6.3.3 Split Ring Resonators (SRRs); 6.4 Simulations of Band-Notching Technique; 6.5 Conclusion; Acknowledgements; References; 7 Real-Time Simulation Design for Continuous Process Industries; 7.1 Introduction; 7.2 Literature Survey and Related Work; 7.3 Simulation Software Architecture; 7.3.1 Trainer Console; 7.3.2 Trainee Stations; 7.4 Simulation System Components; 7.4.1 Communication Methods; 7.4.2 Simulation Interface; 7.5 Process Model Design and Execution; 7.5.1 Data Server and Variables; 7.5.2 Process Rule Configuration

7.5.3 Computational Block Library7.5.4 Predictive Control Blocks; 7.5.5 Fuzzy Blocks Configuration; 7.5.6 Neural Network (NN) prediction; 7.5.7 Model Predictive Control (MPC) Blocks; 7.5.8 Real-Time Tuning and Validation of Simulation Block; 7.5.9 Training the Prediction Network; 7.5.10 Result Analysis; 7.6 Conclusion and Future Research; References; 8 Performance Enhancement of LTE HetNet Using EVM-Based Constellation Combiner (ECC) in WARP; 8.1 Introduction; 8.2 LTE HetNet Network; 8.2.1 System Model; 8.2.2 Transceiver Chain; 8.2.2.1 Transmitter; 8.2.2.2 Receiver