Preface; Acknowledgements; Contents; 1 Introduction; 1.1 Introduction of Microfluidic Biochip Platforms; 1.2 Overview of Flow-Based Microfluidic Biochips; 1.2.1 Structure and Fabrication; 1.2.2 Components; 1.2.3 Applications; 1.3 Challenges and Motivation; 1.3.1 Design Automation; 1.3.2 Contamination Removal; 1.3.3 Defects and Erroneous Operations; 1.4 Outline of the Book; References; 2 Control-Layer Optimization; 2.1 Motivation and Related Prior Work; 2.2 Problem Description, Design Requirements, and Challenges; 2.2.1 Pressure-Propagation Delay; 2.2.2 Requirements in Control-Layer Design

2.2.3 Valve Addressing2.2.4 Routing of Control Channels; 2.2.5 Placement of Control Pins; 2.2.6 Relationship Between Control-Layer Optimization and Clock-Tree Design in VLSI Circuits; 2.3 Problem Formulation; 2.4 Algorithm Design; 2.4.1 Routing Algorithm 1; 2.4.2 Routing Algorithm 2; 2.5 Experimental Results; 2.5.1 Experiments with Two Fabricated Biochips; 2.5.2 Experiments with Synthetic Benchmarks; 2.6 Conclusions; References; 3 Wash Optimization for Cross-Contamination Removal; 3.1 Motivation and Challenges; 3.2 Problem Description and Formulation

3.2.1 Physical Implementability of a Wash Path3.2.2 Execution Time for a Wash Path; 3.3 Search for a Set of Washing Paths; 3.3.1 Generation of the Path Dictionary; 3.3.2 Storage of the Path Dictionary; 3.3.3 Identification of Washing-Path Set; 3.3.4 Washing of Multiple Contaminant Species; 3.3.5 Complexity Analysis; 3.4 Results: Application to Fabricated Biochips; 3.4.1 Results for ChIP; 3.4.2 A Programmable Microfluidic Device with an 8-by-8 Grid; 3.5 Conclusions; References; 4 Fault Modeling, Testing, and Design for Testability; 4.1 Motivation and Challenges

4.2 Defects and Fault Modeling4.3 Testing Strategy; 4.4 Applications to Fabricated Biochip; 4.4.1 Logic Circuit Model; 4.4.2 Test-Pattern Generation and Results; 4.5 Automated Generation of Logic-Circuit Model; 4.5.1 Physical Representation of Boolean Gates in Netlists; 4.5.2 Hierarchical Modeling; 4.5.3 Fault Analysis Based on ATPG Results; 4.6 Other Practical Concerns; 4.6.1 Test Cost; 4.6.2 Dynamic Faults; 4.6.3 Multiple Faults; 4.7 Experimental Demonstration; 4.7.1 Experimental Feasibility Demonstration; 4.7.2 Pattern Set-up Time, Measurement Time and Refresh Time

4.7.3 Experimental Demonstration I: Cell Culture Chip4.7.4 Experimental Demonstration II: WGA Chip; 4.8 Untestable Faults and Design-For-Testability; 4.8.1 Causes of Untestable Faults; 4.8.2 DfT for Flow-Based Microfluidic Biochips; 4.8.3 Demonstration of Proposed DfT Approach; 4.9 Conclusion; References; 5 Techniques for Fault Diagnosis; 5.1 Motivation and Challenges; 5.2 Problem Description; 5.2.1 Single-Defect-Type Assumption; 5.2.2 Syndrome Analysis; 5.2.3 Formulation as a Hitting-Set Problem; 5.3 Algorithm Design; 5.3.1 Complexity Analysis; 5.4 Results: Application to Fabricated Biochips