000780775 000__ 05238cam\a2200565Ii\4500 000780775 001__ 780775 000780775 005__ 20230306143158.0 000780775 006__ m\\\\\o\\d\\\\\\\\ 000780775 007__ cr\nn\nnnunnun 000780775 008__ 170411s2017\\\\si\\\\\\ob\\\\000\0\eng\d 000780775 019__ $$a982161090$$a982226040$$a982344454$$a982423461$$a982587793$$a982818370$$a983071504$$a983325926 000780775 020__ $$a9789811027208$$q(electronic book) 000780775 020__ $$a981102720X$$q(electronic book) 000780775 020__ $$z9789811027192 000780775 020__ $$z9811027196 000780775 035__ $$aSP(OCoLC)ocn982121293 000780775 035__ $$aSP(OCoLC)982121293$$z(OCoLC)982161090$$z(OCoLC)982226040$$z(OCoLC)982344454$$z(OCoLC)982423461$$z(OCoLC)982587793$$z(OCoLC)982818370$$z(OCoLC)983071504$$z(OCoLC)983325926 000780775 040__ $$aN$T$$beng$$erda$$epn$$cN$T$$dN$T$$dGW5XE$$dEBLCP$$dYDX$$dOCLCF$$dUAB 000780775 049__ $$aISEA 000780775 050_4 $$aTK7874.887 000780775 08204 $$a621.3$$223 000780775 1001_ $$aKaushik, Brajesh Kumar. 000780775 24510 $$aNext generation spin torque memories /$$cBrajesh Kumar Kaushik, Shivam Verma, Anant Aravind Kulkarni, Sanjay Prajapati. 000780775 264_1 $$aSingapore :$$bSpringer,$$c[2017] 000780775 300__ $$a1 online resource. 000780775 336__ $$atext$$btxt$$2rdacontent 000780775 337__ $$acomputer$$bc$$2rdamedia 000780775 338__ $$aonline resource$$bcr$$2rdacarrier 000780775 4901_ $$aSpringerBriefs in applied sciences and technology 000780775 504__ $$aIncludes bibliographical references. 000780775 5050_ $$aPreface; Contents; About the Authors; 1 Emerging Memory Technologies; 1.1 Introduction; 1.2 Non-volatile Memories; 1.2.1 Phase Change Memory; 1.2.2 Resistive RAM; 1.2.3 Ferroelectric RAM; 1.2.4 Magnetoresistive RAM; 1.3 Spin Torque Based Memories; 1.3.1 Spin Transfer Torque MRAM; 1.3.2 Spin Orbit Torque MRAM; 1.3.3 Domain Wall MRAM; 1.4 Comparison of Emerging Memory Technologies; 1.5 Chapter Summary; References; 2 Next Generation 3-D Spin Transfer Torque Magneto-resistive Random Access Memories; 2.1 Overview of Conventional STT MRAM: Architecture and Operation; 2.2 Cell Size in Memories 000780775 5058_ $$a2.3 Next Generation 4F2 STT MRAM2.3.1 Proposed Architecture; 2.3.2 Performance Parameters and Windows; 2.3.3 Simulation Framework; 2.4 Case Study; 2.4.1 TCAD Analysis; 2.4.2 TCAD Simulation Setup; 2.4.3 Mixed-Mode Simulation Results; 2.4.4 Impact of High-k GAA Devices; 2.4.5 Impact of High-k GD on Delay; 2.5 Proposed Fabrication Methodology; 2.6 Conclusion; References; 3 Spin Orbit Torque MRAM; 3.1 Introduction; 3.2 SOT Device Structure; 3.3 SOT-MRAM Bit-Cell and Array Architectures; 3.4 SOT-MRAM Write and Read Mechanisms; 3.4.1 Concept of Simultaneous Read and Write Operations 000780775 5058_ $$a3.5 Compact Modeling of the SOT-MTJ Device3.5.1 Magnetization Dynamics; 3.5.2 TMR; 3.6 Design Aspects and Performance Optimization of SOT-MRAM; 3.7 Comparative Analysis of STT-MRAM and SOT-MRAM; References; 4 Multilevel Cell MRAMs; 4.1 Introduction; 4.2 Issues with Single Level Cell (SLC) STT-/SOT-MRAM; 4.3 Multilevel Cell (MLC) Configurations; 4.3.1 STT Based MLC Configurations; 4.3.2 SOT Based MLC Configurations; 4.4 Multilevel Cell (MLC) MRAM Operations; 4.4.1 MLC STT-MRAM Write and Read Operations; 4.4.2 MLC SOT-MRAM Write and Read Operation; 4.5 Modeling and Simulation of MLC MRAMs 000780775 5058_ $$a4.5.1 Simulations of MLC MRAMs4.6 Design Aspects and Optimization of MLC MRAMs; 4.6.1 sMLC MRAMs; 4.6.2 pMLC MRAMs; 4.7 Conclusions; References; 5 Magnetic Domain Wall Race Track Memory; 5.1 Introduction; 5.1.1 Limitations of Existing and Emerging Memory Technologies; 5.2 Fundamentals of Domain-Wall Motion in Nanowire; 5.2.1 Magnetic Domains in Magnetic Nanowire; 5.2.2 Domain-Wall Motion in Nanowire; 5.2.3 Optimization of Domain Wall Motion; 5.3 Domain Wall MRAM; 5.3.1 DW-MRAM Write and Read Operations; 5.4 Racetrack Memory; 5.4.1 Structure of Racetrack Memory; 5.4.2 Write and Read Operations 000780775 5058_ $$a5.5 Racetrack Memory Based Logic Implementations5.6 Chapter Summary; References 000780775 506__ $$aAccess limited to authorized users. 000780775 520__ $$aThis book offers detailed insights into spin transfer torque (STT) based devices, circuits and memories. Starting with the basic concepts and device physics, it then addresses advanced STT applications and discusses the outlook for this cutting-edge technology. It also describes the architectures, performance parameters, fabrication, and the prospects of STT based devices. Further, moving from the device to the system perspective it presents a non-volatile computing architecture composed of STT based magneto-resistive and all-spin logic devices and demonstrates that efficient STT based magneto-resistive and all-spin logic devices can turn the dream of instant on/off non-volatile computing into reality. 000780775 588__ $$aVendor-supplied metadata. 000780775 650_0 $$aSpintronics. 000780775 650_0 $$aNanotechnology. 000780775 650_0 $$aMicroelectronics. 000780775 7001_ $$aVerma, Shivam$$c(Writer on microelectronics) 000780775 7001_ $$aKulkarni, Anant Aravind. 000780775 7001_ $$aPrajapati, Sanjay. 000780775 77608 $$iPrint version:$$z9789811027192$$z9811027196$$w(OCoLC)957509675 000780775 830_0 $$aSpringerBriefs in applied sciences and technology. 000780775 852__ $$bebk 000780775 85640 $$3SpringerLink$$uhttps://univsouthin.idm.oclc.org/login?url=http://link.springer.com/10.1007/978-981-10-2720-8$$zOnline Access$$91397441.1 000780775 909CO $$ooai:library.usi.edu:780775$$pGLOBAL_SET 000780775 980__ $$aEBOOK 000780775 980__ $$aBIB 000780775 982__ $$aEbook 000780775 983__ $$aOnline 000780775 994__ $$a92$$bISE