Preface; Contents; About the Editors; Part I State-of-the-Art Architectures and Automation for Data-Analytics; 1 Scaling the Java Virtual Machine on a Many-Core System; 1.1 Introduction; 1.2 Background; 1.2.1 Workload Selection; 1.2.2 Performance Analysis Tools; 1.2.3 Experimental Setup; 1.3 Thread-Local Data Objects; 1.4 Memory Allocators; 1.5 Java Concurrency API; 1.6 Garbage Collection; 1.7 Non-uniform Memory Access (NUMA); 1.8 Conclusion and Future Directions; Appendix; References; 2 Accelerating Data Analytics Kernels with HeterogeneousComputing; 2.1 Introduction; 2.2 Motivation

2.3 Automated Design Space Exploration Flow2.3.1 The Lin-Analyzer Framework; 2.3.2 Framework Overview; 2.3.3 Instrumentation; 2.3.4 Optimized DDDG Generation; 2.3.4.1 Sub-trace Extraction; 2.3.4.2 DDDG Generation & Pre-optimizations; 2.3.5 DDDG Scheduling; 2.3.6 Enabling Design Space Exploration; 2.4 Acceleration of Data Analytics Kernels; 2.4.1 Estimation Accuracy; 2.4.1.1 Loop Unrolling and Loop Pipelining; 2.4.1.2 Array Partitioning; 2.4.2 Rapid Design Space Exploration; 2.5 Conclusion; References

3 Least-squares-solver Based Machine Learning Acceleratorfor Real-time Data Analytics in Smart Buildings3.1 Introduction; 3.2 IoT System Based Smart Building; 3.2.1 Smart-Grid Architecture; 3.2.2 Smart Gateway for Real-Time Data Analytics; 3.2.3 Problem Formulation for Data Analytics; 3.3 Background on Neural Network Based Machine Learning; 3.3.1 Backward Propagation for Training; 3.3.2 Least-Squares Solver for Training; 3.3.3 Feature Extraction with Behavior Cognition; 3.4 Least-Squares Solver Based Training Algorithm; 3.4.1 Regularized 2-Norm; 3.4.2 Square-Root-Free Cholesky Decomposition

3.4.3 Incremental Least-Squares Solution3.5 Least-Squares Based Machine Learning Accelerator Architecture; 3.5.1 Overview of Computing Flow and Communication; 3.5.2 FPGA Accelerator Architecture; 3.5.3 2-Norm Solver; 3.5.4 Matrix-Vector Multiplication; 3.6 Experiment Results; 3.6.1 Experiment Setup and Benchmark; 3.6.2 FPGA Design Platform and CAD Flow; 3.6.3 Scalable and Parameterized Accelerator Architecture; 3.6.4 Performance for Data Classification; 3.6.5 Performance for Load Forecasting; 3.6.6 Performance Comparisons with Other Platforms; 3.7 Conclusion; References

4 Compute-in-Memory Architecture for Data-Intensive Kernels4.1 Introduction; 4.2 Malleable Hardware Acceleration; 4.2.1 Hardware Architecture; 4.2.2 Application Mapping; 4.2.2.1 Application Description Using an Instruction Set Architecture; 4.2.2.2 Application Mapping to the General Framework; 4.2.3 Domain Customization for Efficient Acceleration; 4.3 Case Studies for Memory-Centric Computing; 4.3.1 MAHA for Security Applications; 4.3.1.1 Domain Exploration; 4.3.1.2 Architecture Description; 4.3.1.3 Results and Comparison to Other Platforms; 4.3.2 MAHA for Text Mining Applications