000798395 000__ 04574cam\a2200505Ia\4500 000798395 001__ 798395 000798395 005__ 20230306143522.0 000798395 006__ m\\\\\o\\d\\\\\\\\ 000798395 007__ cr\un\nnnunnun 000798395 008__ 170905s2017\\\\sz\\\\\\ob\\\\001\0\eng\d 000798395 019__ $$a1002418478$$a1003063180 000798395 020__ $$a9783319597829$$q(electronic book) 000798395 020__ $$a3319597825$$q(electronic book) 000798395 020__ $$z9783319597812 000798395 020__ $$z3319597817 000798395 035__ $$aSP(OCoLC)on1002899075 000798395 035__ $$aSP(OCoLC)1002899075$$z(OCoLC)1002418478$$z(OCoLC)1003063180 000798395 040__ $$aYDX$$beng$$cYDX$$dN$T$$dEBLCP$$dN$T$$dGW5XE$$dUAB 000798395 049__ $$aISEA 000798395 050_4 $$aQA268 000798395 08204 $$a005.7/17$$223 000798395 1001_ $$aGiard, Pascal,$$eauthor. 000798395 24510 $$aHigh-speed decoders for polar codes /$$cPascal Giard, Claude Thibeault, Warren J. Gross. 000798395 260__ $$aCham :$$bSpringer,$$c©2017. 000798395 300__ $$a1 online resource. 000798395 336__ $$atext$$btxt$$2rdacontent 000798395 337__ $$acomputer$$bc$$2rdamedia 000798395 338__ $$aonline resource$$bcr$$2rdacarrier 000798395 504__ $$aIncludes bibliographical references and index. 000798395 5058_ $$a3.2.2.1 Generating an Unrolled Decoder 3.2.2.2 Eliminating Superfluous Operations on B-Values; 3.2.2.3 Improved Layout of the a-Memory; 3.2.2.4 Compile-Time Specialization; 3.2.2.5 Architecture-Specific Optimizations; 3.2.2.6 Memory Footprint; 3.2.2.7 Implementation Comparison; 3.3 Implementation on Embedded Processors; 3.4 Implementation on Graphical Processing Units; 3.4.1 Overview of the GPU Architecture and Terminology; 3.4.2 Choosing an Appropriate Number of Threads per Block; 3.4.3 Choosing an Appropriate Number of Blocks per Kernel; 3.4.4 On the Constituent Codes Implemented 000798395 5050_ $$aPreface; Origin; Scope; Organization; Audience; Acknowledgements; Contents; Acronyms; 1 Polar Codes; 1.1 Construction; 1.2 Tree Representation; 1.3 Systematic Coding; 1.4 Successive-Cancellation Decoding; 1.5 Simplified Successive-Cancellation Decoding; 1.5.1 Rate-0 Nodes; 1.5.2 Rate-1 Nodes; 1.5.3 Rate-R Nodes; 1.6 Fast-SSC Decoding; 1.6.1 Repetition Codes; 1.6.2 SPC Codes; 1.6.3 Repetition-SPC Codes; 1.6.4 Other Operations; 1.7 Other SC-Based Decoding Algorithms; 1.7.1 ML-SSC Decoding; 1.7.2 Hybrid ML-SC Decoding; 1.8 Other Decoding Algorithms; 1.8.1 Belief-Propagation Decoding 000798395 5058_ $$a1.8.2 List-Based Decoding1.9 SC-Based Decoder Hardware Implementations; 1.9.1 Processing Element for SC Decoding; 1.9.2 Semi-Parallel Decoder; 1.9.3 Two-Phase Decoder; 1.9.4 Processor-Like Decoder or the Original Fast-SSC Decoder; 1.9.5 Implementation Results; 2 Fast Low-Complexity Hardware Decoders for Low-RatePolar Codes; 2.1 Introduction; 2.2 Altering the Code Construction; 2.2.1 Original Construction; 2.2.2 Altered Polar Code Construction; 2.2.3 Proposed Altered Construction; 2.2.3.1 Human-Guided Criteria; 2.2.3.2 Example Results; 2.3 New Constituent Decoders; 2.4 Implementation 000798395 5058_ $$a2.4.1 Quantization2.4.2 Rep1 Node; 2.4.3 High-Level Architecture; 2.4.4 Processing Unit or Processor; 2.5 Results; 2.5.1 Verification Methodology; 2.5.2 Comparison with State-of-the-Art Decoders; 2.6 Conclusion; 3 Low-Latency Software Polar Decoders; 3.1 Introduction; 3.2 Implementation on x86 Processors; 3.2.1 Instruction-Based Decoder; 3.2.1.1 Using Fixed-Point Numbers; 3.2.1.2 Vectorizing the Decoding of Constituent Codes; 3.2.1.3 Data Representation; 3.2.1.4 Architecture-Specific Optimizations; 3.2.1.5 Implementation Comparison; 3.2.2 Unrolled Decoder 000798395 5058_ $$a3.4.5 Shared Memory and Memory Coalescing3.4.6 Asynchronous Memory Transfers and Multiple Streams; 3.4.7 On the Use of Fixed-Point Numbers on a GPU; 3.4.8 Results; 3.5 Energy Consumption Comparison; 3.6 Further Discussion; 3.6.1 On the Relevance of the Instruction-Based Decoders; 3.6.2 On the Relevance of Software Decoders in Comparison to Hardware Decoders; 3.6.3 Comparison with LDPC Codes; 3.7 Conclusion; 4 Unrolled Hardware Architectures for Polar Decoders; 4.1 Introduction; 4.2 State-of-the-Art Architectures with Implementations; 4.3 Architecture, Operations and Processing Nodes 000798395 506__ $$aAccess limited to authorized users. 000798395 650_0 $$aError-correcting codes (Information theory) 000798395 650_0 $$aDecoders (Electronics) 000798395 650_0 $$aCoding theory. 000798395 7001_ $$aThibeault, Claude,$$eauthor. 000798395 7001_ $$aGross, Warren J.,$$eauthor. 000798395 77608 $$iPrint version:$$z9783319597812$$z3319597817$$w(OCoLC)985081311 000798395 852__ $$bebk 000798395 85640 $$3SpringerLink$$uhttps://univsouthin.idm.oclc.org/login?url=http://link.springer.com/10.1007/978-3-319-59782-9$$zOnline Access$$91397441.1 000798395 909CO $$ooai:library.usi.edu:798395$$pGLOBAL_SET 000798395 980__ $$aEBOOK 000798395 980__ $$aBIB 000798395 982__ $$aEbook 000798395 983__ $$aOnline 000798395 994__ $$a92$$bISE