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Table of Contents
Preface; Dataflow Taxonomy; Maxeler; Research Issues; Application Issues; Conclusion; Contents; Part I Research; 1 Maxeler AppGallery Revisited; 1.1 Introduction; 1.2 Maxeler AppGallery; 1.2.1 Data Analytics Category; 1.2.1.1 Sequential Monte Carlo; 1.2.1.2 Real-Time VaR Monitoring; 1.2.1.3 Boosted Decision Tree Classifier; 1.2.1.4 Heston Option Pricer; 1.2.2 Engineering Category; 1.2.2.1 Motion Estimation; 1.2.2.2 Real-time 4k Ultra HD Video; 1.2.2.3 Gzip Compression
1.2.3 Low Latency Transaction Processing Category1.2.3.1 HFTDemo; 1.2.4 Networking Category; 1.2.4.1 High-Speed Packet Capture; 1.2.4.2 Packet Pusher; 1.2.4.3 Low-Latency HTTP Web Server; 1.2.5 Science Category; 1.2.5.1 Reverse Time Migration; 1.2.5.2 Network Sorting; 1.2.5.3 Localization Microscopy; 1.2.6 Security Category; 1.2.6.1 Fully Homomorphic Encryption; References; 2 Discrepancy Reduction Between the Topology of Dataflow Graph and the Topology of FPGA Structure; 2.1 Introduction; 2.2 Dataflow Graph
2.3 Getting to Accelerated Application: Maxeler Way2.4 Simulation Debugging; 2.4.1 Simulation Watches; 2.4.2 Simulation printf; 2.5 Hardware Debugging; 2.5.1 DFE printf; 2.6 Advanced Debugging; 2.6.1 Introduction; 2.6.2 Kernel Halted on Input; 2.6.3 Kernel Halted on Output; 2.6.4 Stream Status Blocks; 2.6.5 Deadlock; 2.6.5.1 Deadlock Due To: Kernel Has Scheduled an Input Before an Output; 2.6.5.2 Deadlock Due to: FIFO Ends Up Full; 2.7 Effects of Inconsistency Between Simulation and Hardware; 2.7.1 Uninitialized Elements
2.7.2 Race Condition2.8 Embedded DFE Optimizations; 2.8.1 Kernel Optimizations; 2.8.1.1 Holistic Optimization; 2.8.1.2 Push-Pop Optimizations; 2.8.1.3 Placement Constraints; 2.8.1.4 Input Registering; 2.8.1.5 Per-Stream Optimizations; 2.8.2 Manager Optimizations; 2.8.2.1 LMem Clock Frequency; 2.8.2.2 Stream Clock Frequency; 2.9 Global DFE Optimization Practices: Getting Maximum Performance; 2.9.1 Introduction; 2.9.2 Dataflow Computing Strategy; 2.9.3 Fitting Procedure; 2.9.3.1 Techniques to Fit Designs Onto DFE
2.9.4 How to Make it Fit?2.9.4.1 Stage 1: DFE Logic Utilization >100%: Macro-optimization; 2.9.4.2 Stage 2: DFE Logic Utilization >80% and <100%, Micro-optimizations; 2.9.4.3 Stage 3: DFE Logic Utilization <80%, Frequency Optimization; 2.9.5 Optimizing Memory Bound Applications: Data Size; 2.9.5.1 Differences in Memory Controllers of Different Cards; 2.9.5.2 Data-Specific Compression; 2.9.5.3 Data Encoding; 2.9.5.4 Reorganization of the Order of Computations; 2.9.6 Optimizing Compute Performance: Clock Frequency
1.2.3 Low Latency Transaction Processing Category1.2.3.1 HFTDemo; 1.2.4 Networking Category; 1.2.4.1 High-Speed Packet Capture; 1.2.4.2 Packet Pusher; 1.2.4.3 Low-Latency HTTP Web Server; 1.2.5 Science Category; 1.2.5.1 Reverse Time Migration; 1.2.5.2 Network Sorting; 1.2.5.3 Localization Microscopy; 1.2.6 Security Category; 1.2.6.1 Fully Homomorphic Encryption; References; 2 Discrepancy Reduction Between the Topology of Dataflow Graph and the Topology of FPGA Structure; 2.1 Introduction; 2.2 Dataflow Graph
2.3 Getting to Accelerated Application: Maxeler Way2.4 Simulation Debugging; 2.4.1 Simulation Watches; 2.4.2 Simulation printf; 2.5 Hardware Debugging; 2.5.1 DFE printf; 2.6 Advanced Debugging; 2.6.1 Introduction; 2.6.2 Kernel Halted on Input; 2.6.3 Kernel Halted on Output; 2.6.4 Stream Status Blocks; 2.6.5 Deadlock; 2.6.5.1 Deadlock Due To: Kernel Has Scheduled an Input Before an Output; 2.6.5.2 Deadlock Due to: FIFO Ends Up Full; 2.7 Effects of Inconsistency Between Simulation and Hardware; 2.7.1 Uninitialized Elements
2.7.2 Race Condition2.8 Embedded DFE Optimizations; 2.8.1 Kernel Optimizations; 2.8.1.1 Holistic Optimization; 2.8.1.2 Push-Pop Optimizations; 2.8.1.3 Placement Constraints; 2.8.1.4 Input Registering; 2.8.1.5 Per-Stream Optimizations; 2.8.2 Manager Optimizations; 2.8.2.1 LMem Clock Frequency; 2.8.2.2 Stream Clock Frequency; 2.9 Global DFE Optimization Practices: Getting Maximum Performance; 2.9.1 Introduction; 2.9.2 Dataflow Computing Strategy; 2.9.3 Fitting Procedure; 2.9.3.1 Techniques to Fit Designs Onto DFE
2.9.4 How to Make it Fit?2.9.4.1 Stage 1: DFE Logic Utilization >100%: Macro-optimization; 2.9.4.2 Stage 2: DFE Logic Utilization >80% and <100%, Micro-optimizations; 2.9.4.3 Stage 3: DFE Logic Utilization <80%, Frequency Optimization; 2.9.5 Optimizing Memory Bound Applications: Data Size; 2.9.5.1 Differences in Memory Controllers of Different Cards; 2.9.5.2 Data-Specific Compression; 2.9.5.3 Data Encoding; 2.9.5.4 Reorganization of the Order of Computations; 2.9.6 Optimizing Compute Performance: Clock Frequency