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Table of Contents
1 The Landscape of SoC and IP Security; 1.1 Introduction; 1.2 SoC Design Supply Chain and Security Assets; 1.3 The Challenge of Design Complexity; 1.4 State of Security Design and Validation: Research and Practice; 1.5 The Book; References; 2 Security Validation in Modern SoC Designs; 2.1 Security Needs in Modern SoC Designs; 2.2 Supply Chain Security Threats; 2.3 Security Policies: Requirements from Design; 2.4 Adversaries in SoC Security; 2.5 IP-Level Trust Validation; 2.6 Security Along SoC Design Life Cycle; 2.7 Security Validation Activities; 2.8 Validation Technologies.
2.9 SummaryReferences; 3 SoC Security and Debug; 3.1 Introduction; 3.2 SoC Debug Architecture; 3.2.1 Debug Interface; 3.2.2 On-Chip DfD Instrumentation; 3.3 Security Concerns and Hazards; 3.3.1 SoC Security Requirements; 3.3.2 DfD Induced Security Hazards; 3.4 Protection Against Hazards Induced by Debugging; 3.4.1 Trade-Off Between Security and Debug; 3.4.2 Authentication-Based Debug Access Control; 3.4.3 Limitations and Challenges; 3.5 Summary; References; 4 IP Trust: The Problem and Design/Validation-Based Solution; 4.1 Introduction; 4.2 Design for IP Protection; 4.2.1 Threat Model.
4.2.2 Combinational Logic Locking/Encryption4.2.3 Finite State Machine Locking/Encryption; 4.2.4 Protection Methods for FPGA IP; 4.3 IP Certification; 4.4 Conclusion; References; 5 Security of Crypto IP Core: Issues and Countermeasures; 5.1 Introduction; 5.1.1 Implementation: An Issue for Security; 5.1.2 Side Channels; 5.2 Power Analysis of Cryptographic Cores; 5.2.1 Simple Power Attack (SPA); 5.2.2 Differential Power Attacks; 5.2.3 Template Attack; 5.3 Countermeasures Against Power Analysis; 5.3.1 t-Private Circuit; 5.3.2 Masking; 5.3.3 DRECON: DPA Resistant Encryption by Construction.
5.3.4 Evaluation of Side Channel Leakage for a Crypto Core5.4 Fault Attack Resistant Crypto Cores; 5.4.1 General Principle of DFA of Block Ciphers; 5.4.2 Fault Analysis of AES; 5.4.3 Experimental Results on Fault Models; 5.4.4 Proposed DFA on AES-192 Key Schedule ; 5.4.5 Countermeasures Against DFA; 5.5 Testing and Validation of Crypto Cores; 5.5.1 Working Principle of Scan-Chain-Attacks on Block Ciphers; 5.6 Conclusions; References; 6 PUF-Based Authentication; 6.1 Introduction; 6.2 Information Security and Cryptography; 6.3 Cryptographic Primitives for Authentication Protocols.
6.3.1 Random Number Generation6.3.2 Cryptographic Hash Functions; 6.3.3 Secure Sketches and Fuzzy Extractors; 6.3.4 Statistical Metrics; 6.4 Traditional, Software-Oriented Authentication; 6.4.1 Entity Authentication; 6.5 Physical Unclonable Functions (PUFs); 6.5.1 PUF-Based Authentication; 6.5.2 Strong Versus Weak PUFs; 6.5.3 The Arbiter PUF; 6.5.4 Hardware-Embedded Delay PUF (HELP); Clock Strobing; PN Processing; Temperature-Voltage (TV) Compensation; Bit Generation Algorithm; Entropy Analysis; Statistical Analysis of the Bitstrings; Security Property Analysis.
2.9 SummaryReferences; 3 SoC Security and Debug; 3.1 Introduction; 3.2 SoC Debug Architecture; 3.2.1 Debug Interface; 3.2.2 On-Chip DfD Instrumentation; 3.3 Security Concerns and Hazards; 3.3.1 SoC Security Requirements; 3.3.2 DfD Induced Security Hazards; 3.4 Protection Against Hazards Induced by Debugging; 3.4.1 Trade-Off Between Security and Debug; 3.4.2 Authentication-Based Debug Access Control; 3.4.3 Limitations and Challenges; 3.5 Summary; References; 4 IP Trust: The Problem and Design/Validation-Based Solution; 4.1 Introduction; 4.2 Design for IP Protection; 4.2.1 Threat Model.
4.2.2 Combinational Logic Locking/Encryption4.2.3 Finite State Machine Locking/Encryption; 4.2.4 Protection Methods for FPGA IP; 4.3 IP Certification; 4.4 Conclusion; References; 5 Security of Crypto IP Core: Issues and Countermeasures; 5.1 Introduction; 5.1.1 Implementation: An Issue for Security; 5.1.2 Side Channels; 5.2 Power Analysis of Cryptographic Cores; 5.2.1 Simple Power Attack (SPA); 5.2.2 Differential Power Attacks; 5.2.3 Template Attack; 5.3 Countermeasures Against Power Analysis; 5.3.1 t-Private Circuit; 5.3.2 Masking; 5.3.3 DRECON: DPA Resistant Encryption by Construction.
5.3.4 Evaluation of Side Channel Leakage for a Crypto Core5.4 Fault Attack Resistant Crypto Cores; 5.4.1 General Principle of DFA of Block Ciphers; 5.4.2 Fault Analysis of AES; 5.4.3 Experimental Results on Fault Models; 5.4.4 Proposed DFA on AES-192 Key Schedule ; 5.4.5 Countermeasures Against DFA; 5.5 Testing and Validation of Crypto Cores; 5.5.1 Working Principle of Scan-Chain-Attacks on Block Ciphers; 5.6 Conclusions; References; 6 PUF-Based Authentication; 6.1 Introduction; 6.2 Information Security and Cryptography; 6.3 Cryptographic Primitives for Authentication Protocols.
6.3.1 Random Number Generation6.3.2 Cryptographic Hash Functions; 6.3.3 Secure Sketches and Fuzzy Extractors; 6.3.4 Statistical Metrics; 6.4 Traditional, Software-Oriented Authentication; 6.4.1 Entity Authentication; 6.5 Physical Unclonable Functions (PUFs); 6.5.1 PUF-Based Authentication; 6.5.2 Strong Versus Weak PUFs; 6.5.3 The Arbiter PUF; 6.5.4 Hardware-Embedded Delay PUF (HELP); Clock Strobing; PN Processing; Temperature-Voltage (TV) Compensation; Bit Generation Algorithm; Entropy Analysis; Statistical Analysis of the Bitstrings; Security Property Analysis.