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Table of Contents
Preface; Contents; Part I Unconventional Number Representations: Arithmetic Units and Processor Design; 1 Introduction to Residue Number System: Structure and Teaching Methodology; 1.1 Introduction; 1.2 RNS Structure; 1.3 RNS Teaching Methodology; 1.3.1 Basic Concepts; 1.3.2 Modular Adders and Multipliers; 1.3.3 Forward Converter; 1.3.4 Reverse Converter; 1.3.5 Application: RNS-Based Embedded Systems Design; 1.3.6 Hard RNS Operations; 1.3.7 ASIC/FPGA Implementation; 1.4 Conclusion; References; 2 RNS-Based Embedded Processor Design; 2.1 Introduction; 2.2 Processor Architecture.
2.3 Instruction Set Architecture2.4 RNS Arithmetic Operations; 2.4.1 Binary-to-RNS Conversion; 2.4.2 Arithmetic Channels; 2.4.2.1 Modulo {2n-k}; 2.4.2.2 Modulo {2n+k}; 2.4.2.3 Proposed Arithmetic Structures; 2.4.3 RNS-to-Binary Conversion; 2.4.3.1 Proposed CRT Approach; 2.4.3.2 Proposed MRC Approach; 2.5 Control Units; 2.6 State-of-the-Art Analysis; 2.6.1 State of the Art; 2.6.2 Analysis Based on the Arithmetic Units; 2.7 Summary; References; 3 Non-Modular Operations of the Residue Number System: Functions for Computing; Nomenclature; 3.1 Introduction; 3.2 Non-Modular Operation in the RNS.
3.2.1 Mixed-Radix Conversion3.2.2 Chinese Remainder Theorem; 3.3 The 'Diagonal Function' of the RNS; 3.4 The 'Quotient Function' of the RNS; 3.5 Performance Analysis; 3.6 Conclusion; References; 4 Fault-Tolerant Computing in Redundant Residue Number System; 4.1 Motivations; 4.2 Background and Preliminaries; 4.2.1 Residue Number System; 4.2.2 Residue Arithmetic; 4.2.3 Residue-to-Binary Conversion; 4.3 Redundant Residue Number System; 4.4 Single Residue Digit Error Detectionand Correction Algorithms; 4.5 Multiple Residue Digit Error Detection and Correction Algorithms.
4.6 Applications of RRNS Codes in Error Detection and Correction4.7 Summary; References; 5 Decimal Floating Point Number System; 5.1 Need for Decimal Floating Point Formats; 5.2 Representation of Decimal Digits; 5.3 Decimal Addition; 5.3.1 Floating Point Addition; 5.3.2 Specific Designs; 5.4 Decimal Multiplication; 5.4.1 Floating Point Multiplication; 5.4.2 Specific Designs; 5.5 Decimal Fused Multiply Add (FMA); 5.5.1 Floating Point FMA; 5.5.2 Specific Designs; 5.6 Decimal Division; 5.6.1 Floating Point Division; 5.6.2 Specific Designs; 5.7 Decimal Square Root and Other Functions.
5.8 Verification5.9 Potential Embedded Systems Applications; 5.10 Conclusion; References; 6 Design and Evaluation of Booth-Encoded Multipliers in Redundant Binary Representation; 6.1 Introduction; 6.2 Booth Multiplier Design in Redundant Binary Representation; 6.2.1 Redundant Binary Arithmetic and Carry-Free Adding Rule; 6.2.2 Booth Algorithms in Redundant Binary Multiplier; 6.2.3 Redundant Binary Coding Interface Components; 6.2.4 Review of Existing RB Multipliers; 6.3 Architectural Exploration on Redundant Binary Booth Multipliers.
2.3 Instruction Set Architecture2.4 RNS Arithmetic Operations; 2.4.1 Binary-to-RNS Conversion; 2.4.2 Arithmetic Channels; 2.4.2.1 Modulo {2n-k}; 2.4.2.2 Modulo {2n+k}; 2.4.2.3 Proposed Arithmetic Structures; 2.4.3 RNS-to-Binary Conversion; 2.4.3.1 Proposed CRT Approach; 2.4.3.2 Proposed MRC Approach; 2.5 Control Units; 2.6 State-of-the-Art Analysis; 2.6.1 State of the Art; 2.6.2 Analysis Based on the Arithmetic Units; 2.7 Summary; References; 3 Non-Modular Operations of the Residue Number System: Functions for Computing; Nomenclature; 3.1 Introduction; 3.2 Non-Modular Operation in the RNS.
3.2.1 Mixed-Radix Conversion3.2.2 Chinese Remainder Theorem; 3.3 The 'Diagonal Function' of the RNS; 3.4 The 'Quotient Function' of the RNS; 3.5 Performance Analysis; 3.6 Conclusion; References; 4 Fault-Tolerant Computing in Redundant Residue Number System; 4.1 Motivations; 4.2 Background and Preliminaries; 4.2.1 Residue Number System; 4.2.2 Residue Arithmetic; 4.2.3 Residue-to-Binary Conversion; 4.3 Redundant Residue Number System; 4.4 Single Residue Digit Error Detectionand Correction Algorithms; 4.5 Multiple Residue Digit Error Detection and Correction Algorithms.
4.6 Applications of RRNS Codes in Error Detection and Correction4.7 Summary; References; 5 Decimal Floating Point Number System; 5.1 Need for Decimal Floating Point Formats; 5.2 Representation of Decimal Digits; 5.3 Decimal Addition; 5.3.1 Floating Point Addition; 5.3.2 Specific Designs; 5.4 Decimal Multiplication; 5.4.1 Floating Point Multiplication; 5.4.2 Specific Designs; 5.5 Decimal Fused Multiply Add (FMA); 5.5.1 Floating Point FMA; 5.5.2 Specific Designs; 5.6 Decimal Division; 5.6.1 Floating Point Division; 5.6.2 Specific Designs; 5.7 Decimal Square Root and Other Functions.
5.8 Verification5.9 Potential Embedded Systems Applications; 5.10 Conclusion; References; 6 Design and Evaluation of Booth-Encoded Multipliers in Redundant Binary Representation; 6.1 Introduction; 6.2 Booth Multiplier Design in Redundant Binary Representation; 6.2.1 Redundant Binary Arithmetic and Carry-Free Adding Rule; 6.2.2 Booth Algorithms in Redundant Binary Multiplier; 6.2.3 Redundant Binary Coding Interface Components; 6.2.4 Review of Existing RB Multipliers; 6.3 Architectural Exploration on Redundant Binary Booth Multipliers.