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Table of Contents
Foreword; Preface; Contents; 1 Introduction; 1.1 Sources of Variability; 1.2 Delay Variation; 1.3 Book Organization; References; Part I Predicting and Preventing Errors; 2 Instruction-Level Tolerance; 2.1 Introduction; 2.2 Effect of Operating Conditions; 2.3 Delay Variation Among Pipeline Stages; 2.4 Instruction Characterization Methodology and Experimental Results; 2.4.1 Gate-Level Simulation; 2.4.2 Instruction-Level Delay Variability; 2.4.3 Less Intrusive Variation-Tolerant Technique; 2.4.4 Power Variability; 2.5 Chapter Summary; References; 3 Sequence-Level Tolerance; 3.1 Introduction.
3.2 PVT Variations3.2.1 Conventional Static Timing Analysis; 3.2.2 Variation-Aware Statistical STA; 3.3 Error-Tolerant Applications; 3.3.1 Analysis of Adaptive Guardbanding for Probabilistic Applications; 3.4 Error-Intolerant Applications; 3.4.1 Sequence-Level Vulnerability (SLV); 3.4.2 SLV Characterization; 3.5 Adaptive Guardbanding; 3.6 Experimental Results; 3.6.1 Effectiveness of Adaptive Guardbanding; 3.6.2 Overhead of Adaptive Guardbanding; 3.7 Chapter Summary; References; 4 Procedure-Level Tolerance; 4.1 Introduction; 4.2 Variation-Tolerant Processor Clusters Architecture.
4.2.1 Variation-Aware VDD-Hopping4.3 Procedure Hopping for Dynamic IR-Drop; 4.3.1 Supporting Intra-cluster Procedure Hopping; 4.4 Characterization of PLV to Dynamic Operating Conditions; 4.5 Experimental Results; 4.5.1 Cost of Procedure Hopping; 4.6 Chapter Summary; References; 5 Kernel-Level Tolerance; 5.1 Introduction; 5.2 Device-Level NBTI Model; 5.3 GP-GPU Architecture; 5.3.1 GP-GPU Workload Distribution; 5.4 Aging-Aware Compilation; 5.4.1 Observability: Aging Sensors; 5.4.2 Prediction: Wearout Estimation Module; 5.4.3 Controllability: Uniform Slot Assignment; 5.5 Experimental Results.
5.6 Chapter SummaryReferences; 6 Hierarchically Focused Guardbanding; 6.1 Introduction; 6.2 Timing Error Model for PVTA; 6.2.1 Analysis Flow for Timing Error Extraction; 6.2.2 Parametric Model Fitting; 6.2.3 TER Classification; 6.2.4 Robustness of Classification; 6.3 Runtime Hierarchically Focused Guardbanding; 6.3.1 Observability; 6.3.2 Controllability; 6.4 A Case Study of HFG on GPUs; 6.5 Chapter Summary; References; Part II Detecting and Correcting Errors; 7 Work-Unit Tolerance; 7.1 Introduction; 7.2 Architectural Support for VOMP; 7.3 Work-Unit Vulnerability and VOMP Work-Sharing.
7.3.1 Intra- and Inter-corner WUV7.3.2 Online WUV Characterization; 7.4 VOMP Schedulers; 7.4.1 Variation-Aware Task Scheduling (VATS); 7.4.2 Variation-Aware Section Scheduling (VASS); 7.5 Experimental Results; 7.5.1 Framework Setup; 7.5.2 VOMP Results for Tasking; 7.5.3 VOMP Results for Sections; 7.6 Chapter Summary; References; 8 Memristive-Based Associative Memory for Error Recovery; 8.1 Introduction; 8.2 Energy-Efficient GP-GPUs; 8.2.1 Associative Memristive-Based Computing; 8.3 Collaborative Compilation; 8.3.1 FPU Memristive-Based Computing; 8.4 Experimental Results.
3.2 PVT Variations3.2.1 Conventional Static Timing Analysis; 3.2.2 Variation-Aware Statistical STA; 3.3 Error-Tolerant Applications; 3.3.1 Analysis of Adaptive Guardbanding for Probabilistic Applications; 3.4 Error-Intolerant Applications; 3.4.1 Sequence-Level Vulnerability (SLV); 3.4.2 SLV Characterization; 3.5 Adaptive Guardbanding; 3.6 Experimental Results; 3.6.1 Effectiveness of Adaptive Guardbanding; 3.6.2 Overhead of Adaptive Guardbanding; 3.7 Chapter Summary; References; 4 Procedure-Level Tolerance; 4.1 Introduction; 4.2 Variation-Tolerant Processor Clusters Architecture.
4.2.1 Variation-Aware VDD-Hopping4.3 Procedure Hopping for Dynamic IR-Drop; 4.3.1 Supporting Intra-cluster Procedure Hopping; 4.4 Characterization of PLV to Dynamic Operating Conditions; 4.5 Experimental Results; 4.5.1 Cost of Procedure Hopping; 4.6 Chapter Summary; References; 5 Kernel-Level Tolerance; 5.1 Introduction; 5.2 Device-Level NBTI Model; 5.3 GP-GPU Architecture; 5.3.1 GP-GPU Workload Distribution; 5.4 Aging-Aware Compilation; 5.4.1 Observability: Aging Sensors; 5.4.2 Prediction: Wearout Estimation Module; 5.4.3 Controllability: Uniform Slot Assignment; 5.5 Experimental Results.
5.6 Chapter SummaryReferences; 6 Hierarchically Focused Guardbanding; 6.1 Introduction; 6.2 Timing Error Model for PVTA; 6.2.1 Analysis Flow for Timing Error Extraction; 6.2.2 Parametric Model Fitting; 6.2.3 TER Classification; 6.2.4 Robustness of Classification; 6.3 Runtime Hierarchically Focused Guardbanding; 6.3.1 Observability; 6.3.2 Controllability; 6.4 A Case Study of HFG on GPUs; 6.5 Chapter Summary; References; Part II Detecting and Correcting Errors; 7 Work-Unit Tolerance; 7.1 Introduction; 7.2 Architectural Support for VOMP; 7.3 Work-Unit Vulnerability and VOMP Work-Sharing.
7.3.1 Intra- and Inter-corner WUV7.3.2 Online WUV Characterization; 7.4 VOMP Schedulers; 7.4.1 Variation-Aware Task Scheduling (VATS); 7.4.2 Variation-Aware Section Scheduling (VASS); 7.5 Experimental Results; 7.5.1 Framework Setup; 7.5.2 VOMP Results for Tasking; 7.5.3 VOMP Results for Sections; 7.6 Chapter Summary; References; 8 Memristive-Based Associative Memory for Error Recovery; 8.1 Introduction; 8.2 Energy-Efficient GP-GPUs; 8.2.1 Associative Memristive-Based Computing; 8.3 Collaborative Compilation; 8.3.1 FPU Memristive-Based Computing; 8.4 Experimental Results.