Preface; Acknowledgements; Contents; About the Authors; 1 Introduction; 1.1 Why ADC?; 1.1.1 ADC History; 1.1.2 Modern ADC; 1.2 Why This Book?; 1.3 General Concepts; 1.3.1 Nyquist ADC; 1.3.2 Resolution; 1.3.3 Quantization Error; 1.3.4 Static Specifications; 1.3.5 Dynamic Specifications; 1.3.6 Symbol; References; 2 ADC Architecture; 2.1 Introduction; 2.1.1 Traditional Architectures; 2.1.2 Limitations; 2.2 Improved Pipelined ADC; 2.2.1 SHA-less Architecture; 2.2.2 Multi-bit Front End; 2.2.3 Redundancy Technique; 2.3 Improved SAR ADC; 2.3.1 Power-Efficient Architecture.

2.3.2 High-Speed Architecture 2.3.3 Low-Area Architecture ; 2.3.4 Summing up; 2.4 Hybrid ADC; 2.4.1 Subranging SAR ADC; 2.4.2 Pipelined SAR ADC; 2.5 Time-Interleaved ADC; 2.6 Summing up; References; 3 Reference Voltage Buffer; 3.1 Introduction; 3.2 Traditional Reference Voltage Buffer; 3.2.1 Buffer with Off-Chip Capacitor; 3.2.2 Fully Integrated Buffer; 3.3 Improved Reference Voltage Buffer; 3.3.1 Level-Shifter-Aided Buffer; 3.3.2 Charge-Compensation-Based Buffer; 3.4 Summing up; References; 4 Amplification ; 4.1 Introduction; 4.2 Residue Amplification; 4.2.1 Opamp-Based Residue Amplification.

4.2.2 Comparator-Based Residue Amplification4.2.3 Open-Loop Dynamic Amplifier; 4.3 Circuit Technique Aided Opamp; 4.3.1 Correlated Level Shifting; 4.3.2 Range Scaling; 4.3.3 Opamp and Capacitor Sharing; 4.4 Opamp Design; 4.4.1 Traditional Opamp; 4.4.2 Hybrid Opamp; 4.5 Summing up; References; 5 Comparator; 5.1 Introduction; 5.2 Circuit-Technique-Aided Comparator; 5.2.1 Redundancy Technique; 5.2.2 Reference Voltage Stabilization Technique; 5.3 Comparator Design; 5.3.1 Speed and Power Dissipation; 5.3.2 Noise; 5.3.3 Offset; 5.3.4 Kickback Noise; 5.4 Summing up; References; 6 Calibration.

6.1 Introduction6.2 Error Mechanisms; 6.2.1 Errors in Pipelined ADC; 6.2.2 Errors in SAR ADC; 6.2.3 Errors in Flash ADC; 6.2.4 Errors in Time-Interleaved ADC; 6.3 Calibration Principle; 6.4 Calibration Schemes; 6.4.1 Calibration of Pipelined ADC; 6.4.2 Calibration of SAR ADC; 6.4.3 Calibration of Flash ADC; 6.4.4 Calibration of Time-Interleaved ADC; 6.5 Summing up; References; 7 Design Case; 7.1 Introduction; 7.2 ADC Architecture; 7.3 FSSTAGE; 7.3.1 Opamp and Capacitor Sharing; 7.3.2 SHA Less; 7.3.3 Range Scaling; 7.4 Blind Background Calibration; 7.5 Circuit Implementation.

7.5.1 Single-Stage Opamp7.5.2 Level-Shifter-Aided Reference Buffer; 7.5.3 Comparators; 7.5.4 Clock Receiver; 7.6 Measurement Results and Comparisons; 7.7 Summing up; References; 8 Contributions and Future Directions; 8.1 Main Contributions; 8.2 Future Directions; 8.2.1 High-Speed Interface; 8.2.2 Software Radio Application; 8.2.3 Process-Friendly Design; References; Index.