Preface; The Topics Covered Before in This Series; Contents; Part I Hybrid Data Converters; 1 Hybrid Data Converters; 1.1 Introduction; 1.2 The Role of the Analog to Digital Conversion Interface ; 1.3 Abstraction Hierarchy and Concepts in Hybrid Converters; 1.4 Reconfiguration and On-Chip Intelligence; 1.5 Functional and Technology Co-integration in Hybrid Converters; 1.6 Hybrid Analog to Digital Converters Across Speed and Resolution; 1.7 Conclusions; References; 2 Hybrid and Segmented ADC Techniques to Optimize Power Efficiency and Area: The Case of a 0.076 mm2 600 MS/s 12b SAR- ADC

2.1 Introduction2.2 Incremental A Conversion Algorithm; 2.3 SAR-A Subrange Hybrid ADC Architecture; 2.4 Charge-Redistribution SAR-DAC; 2.5 Charge-Sharing SAR-DAC; 2.6 Segmented Charge-Sharing Charge-Redistribution SAR-DAC; 2.7 ADC Architecture and Calibrations; 2.8 Circuit Level Implementation; 2.9 Measurements; 2.10 Conclusions; References; 3 Interleaved Pipelined SAR ADCs: Combined Power for Efficient Accurate High-Speed Conversion; 3.1 Introduction; 3.2 Architecture; 3.2.1 Number of Stages; 3.2.2 Number of Channels; 3.2.3 Error Sources; 3.3 Main Building Blocks; 3.3.1 Sampling Stage

3.3.2 DAC3.3.3 Comparators; 3.3.4 Residue Amplifier; 3.4 Design Examples; 3.5 Conclusions; References; 4 Hybrid VCO Based 0-1 MASH and Hybrid SAR; 4.1 Introduction; 4.2 SAR+VCO 0-1 MASH ADC; 4.2.1 ADC Architecture; 4.2.2 ADC Model; 4.2.3 Measurement Results; 4.3 Hybrid SAR ADC; 4.3.1 Circuit Architecture; 4.3.2 Analysis; 4.3.3 Chip Measurement Results; 4.4 Conclusions; References; 5 A Hybrid Architecture for a Reconfigurable SAR ADC; 5.1 Introduction; 5.2 ADC Architectures and Fundamental Challenges; 5.3 Hybrid Architecture with SAR ADCs; 5.4 DAC Linearization Techniques

5.5 DAC Mismatch Error Shaping for SAR ADCs5.6 General Form of DAC Mismatch Error Shaping Technique; 5.7 Reconfigurable Hybrid SAR ADC; 5.8 Experimental Results; 5.9 Conclusions; References; 6 A Hybrid ADC for High Resolution: The Zoom ADC; 6.1 Introduction; 6.2 Energy Efficiency of High-Resolution DT-SDMs; 6.3 Area Efficiency of High-Resolution ADCs; 6.4 Hybrid ADCs; 6.5 Incremental Zoom ADC; 6.5.1 Dynamic Zoom ADC; 6.5.2 A Dynamic Zoom ADC for Digital Audio; 6.5.3 The SDM: OSR, Loop Filter, and the Quantizer; 6.5.4 The SAR ADC and Over-ranging; 6.5.5 The Overall System; 6.6 Circuit Design

6.7 Measurement Results6.8 Conclusions; References; Part II Smart Sensors for the IoT; 7 Advances in Biomedical Sensor Systems for Wearable Health; 7.1 Introduction; 7.2 ExG Readout Circuits; 7.2.1 Ultralow-Power (ULP) IAs; 7.2.2 High Input Impedance IAs; 7.2.3 Digitally Assisted IAs; 7.3 Bio-impedance Readout Circuits; 7.3.1 Introduction; 7.3.2 Current Generator (CGEN); 7.3.3 BIOZ Channel for Single Frequency; 7.3.4 BIOZ Channel for Multifrequency (MF); 7.4 Photoplethysmogram Readout Circuits; 7.4.1 Introduction; 7.4.2 Ambient Light Cancellation; 7.4.3 A High-DR PPG Readout