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000823973 019__ $$a1013487595
000823973 020__ $$a9783319666198$$q(electronic book)
000823973 020__ $$a3319666193$$q(electronic book)
000823973 020__ $$z9783319666181
000823973 0247_ $$a10.1007/978-3-319-66619-8$$2doi
000823973 035__ $$aSP(OCoLC)on1005978621
000823973 035__ $$aSP(OCoLC)1005978621$$z(OCoLC)1013487595
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000823973 049__ $$aISEA
000823973 050_4 $$aTK7874.66
000823973 08204 $$a621.3815$$223
000823973 1001_ $$aKhondkar, Progyna,$$eauthor.
000823973 24510 $$aLow-power design and power-aware verification /$$cProgyna Khondkar.
000823973 264_1 $$aCham, Switzerland :$$bSpringer,$$c[2018]
000823973 300__ $$a1 online resource :$$billustrations
000823973 336__ $$atext$$btxt$$2rdacontent
000823973 337__ $$acomputer$$bc$$2rdamedia
000823973 338__ $$aonline resource$$bcr$$2rdacarrier
000823973 347__ $$atext file$$bPDF$$2rda
000823973 504__ $$aIncludes bibliographical references.
000823973 5050_ $$a1 Introduction -- 2 Background -- 3 Modeling UPF -- 4 Power Aware Standardization of Library -- 5 UPF Based Power Aware Dynamic Simulation -- 6 Power Aware Dynamic Simulation Coverage -- 7 UPF Based Power Aware Static Verification -- 8 References.
000823973 506__ $$aAccess limited to authorized users.
000823973 520__ $$aUntil now, there has been a lack of a complete knowledge base to fully comprehend Low power (LP) design and power aware (PA) verification techniques and methodologies and deploy them all together in a real design verification and implementation project. This book is a first approach to establishing a comprehensive PA knowledge base. LP design, PA verification, and Unified Power Format (UPF) or IEEE-1801 power format standards are no longer special features. These technologies and methodologies are now part of industry-standard design, verification, and implementation flows (DVIF). Almost every chip design today incorporates some kind of low power technique either through power management on chip, by dividing the design into different voltage areas and controlling the voltages, through PA dynamic and PA static verification, or their combination. The entire LP design and PA verification process involves thousands of techniques, tools, and methodologies, employed from the r egister transfer level (RTL) of design abstraction down to the synthesis or place-and-route levels of physical design. These techniques, tools, and methodologies are evolving everyday through the progression of design-verification complexity and more intelligent ways of handling that complexity by engineers, researchers, and corporate engineering policy makers.
000823973 588__ $$aOnline resource; title from PDF title page (SpringerLink, viewed October 17, 2017).
000823973 650_0 $$aLow voltage integrated circuits$$xDesign and construction.
000823973 77608 $$iPrint version: $$z9783319666181
000823973 852__ $$bebk
000823973 85640 $$3SpringerLink$$uhttps://univsouthin.idm.oclc.org/login?url=http://link.springer.com/10.1007/978-3-319-66619-8$$zOnline Access$$91397441.1
000823973 909CO $$ooai:library.usi.edu:823973$$pGLOBAL_SET
000823973 980__ $$aEBOOK
000823973 980__ $$aBIB
000823973 982__ $$aEbook
000823973 983__ $$aOnline
000823973 994__ $$a92$$bISE