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Intro; Preface; Introduction; Contents; Chapter 1: General Issues of Gate-Level Simulation and Optimization of Digital Circuits with Consideration of Destabilizing Fa...; 1.1 Significance of DF Influence on Functioning of Modern Digital Circuits; 1.1.1 External DF; 1.1.2 Internal DF; 1.2 Analysis of the Current State of Simulation and Optimization of Digital Circuits in Terms of DF Consideration; 1.3 Requirements for Gate-Level Simulation Tools and Optimization of Digital Circuits, Focused on DF Consideration
1.4 Principles of Gate-Level Simulation and Optimization of Digital Circuits with Consideration of DFChapter 2: Models of Logical Elements for DF Consideration; 2.1 Capabilities of MCE to Define Functional Failures; 2.2 Structure of the Model of Considering DF Effects (MCE); 2.2.1 Logic Block of MGE; 2.2.2 Inertia block of MGE; 2.3 Determination of Timing Parameters of the MCE; 2.4 Research of Properties of the MCE; Chapter 3: Models for Determining the Influence of DF; 3.1 Methodology for Constructing Models for Determining the Influence of DF; 3.1.1 The Basic Logic Cell TTL (Fig. 1.13
Tables 3.1, 3.2, 3.3, 3.4, 3.5, 3.6, 3.7)3.1.2 Basic Logical Cell ECL (Fig. 1.14; Tables 3.8, 3.9, 3.10, 3.11, 3.12, 3.13, 3.14); 3.1.3 Basic Logical Cell CMOS (Fig. 1.15; Tables 3.15, 3.16, 3.17, 3.18, 3.19, 3.20, 3.21); 3.1.4 Models of Interconnects; 3.1.5 MDE Noise in Power Rails; 3.2 Models of Noise in Power Lines; 3.3 Calculation and Optimization of the Parameters of Models for Determining the Influence of DF; 3.3.1 Description of the COP Algorithm of the MDE DF; 3.3.2 An Example of the COP Algorithm of MDE DF; 3.4 Models of Circuits with Switched Capacitors
3.4.1 Examples of the Use of Integrated Circuit Models on a SC3.4.2 Improving the Accuracy of Integrated Circuit Models on a SC; Chapter 4: Algorithmic Implementation of the Automated System of Gate-Level Simulation of Digital Circuits with Consideration ...; 4.1 Algorithm of Gate-Level Simulation of Digital Circuits with Consideration of DF; 4.2 Description of the Algorithm; 4.3 Simulation Example; 4.4 Mixed-Mode Simulation Algorithms with Consideration of DF; Chapter 5: Optimization of Digital Circuits with Consideration of DF
5.1 Optimization of Critical Timing Paths of Digital Circuits with Consideration of DF5.2 Algorithm for Optimization of Critical Timing Paths of Digital Circuits with Consideration of DF; 5.3 An example of Optimization of Critical Timing Paths of Digital Circuits with Consideration of DF; 5.4 Optimization of Power Consumption of Digital Circuits with Consideration of DF; Chapter 6: Linguistic and Software Development of the Automated System of Gate-Level Simulation of Digital Circuits with Consi...; 6.1 Software Structure; 6.2 Linguistic Development
1.4 Principles of Gate-Level Simulation and Optimization of Digital Circuits with Consideration of DFChapter 2: Models of Logical Elements for DF Consideration; 2.1 Capabilities of MCE to Define Functional Failures; 2.2 Structure of the Model of Considering DF Effects (MCE); 2.2.1 Logic Block of MGE; 2.2.2 Inertia block of MGE; 2.3 Determination of Timing Parameters of the MCE; 2.4 Research of Properties of the MCE; Chapter 3: Models for Determining the Influence of DF; 3.1 Methodology for Constructing Models for Determining the Influence of DF; 3.1.1 The Basic Logic Cell TTL (Fig. 1.13
Tables 3.1, 3.2, 3.3, 3.4, 3.5, 3.6, 3.7)3.1.2 Basic Logical Cell ECL (Fig. 1.14; Tables 3.8, 3.9, 3.10, 3.11, 3.12, 3.13, 3.14); 3.1.3 Basic Logical Cell CMOS (Fig. 1.15; Tables 3.15, 3.16, 3.17, 3.18, 3.19, 3.20, 3.21); 3.1.4 Models of Interconnects; 3.1.5 MDE Noise in Power Rails; 3.2 Models of Noise in Power Lines; 3.3 Calculation and Optimization of the Parameters of Models for Determining the Influence of DF; 3.3.1 Description of the COP Algorithm of the MDE DF; 3.3.2 An Example of the COP Algorithm of MDE DF; 3.4 Models of Circuits with Switched Capacitors
3.4.1 Examples of the Use of Integrated Circuit Models on a SC3.4.2 Improving the Accuracy of Integrated Circuit Models on a SC; Chapter 4: Algorithmic Implementation of the Automated System of Gate-Level Simulation of Digital Circuits with Consideration ...; 4.1 Algorithm of Gate-Level Simulation of Digital Circuits with Consideration of DF; 4.2 Description of the Algorithm; 4.3 Simulation Example; 4.4 Mixed-Mode Simulation Algorithms with Consideration of DF; Chapter 5: Optimization of Digital Circuits with Consideration of DF
5.1 Optimization of Critical Timing Paths of Digital Circuits with Consideration of DF5.2 Algorithm for Optimization of Critical Timing Paths of Digital Circuits with Consideration of DF; 5.3 An example of Optimization of Critical Timing Paths of Digital Circuits with Consideration of DF; 5.4 Optimization of Power Consumption of Digital Circuits with Consideration of DF; Chapter 6: Linguistic and Software Development of the Automated System of Gate-Level Simulation of Digital Circuits with Consi...; 6.1 Software Structure; 6.2 Linguistic Development