Trusted digital circuits : hardware trojan vulnerabilities, prevention and detection / Hassan Salmani.
Salmani, Hassan, author.
2018
QA76.9.A25
Available Online

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Title Trusted digital circuits : hardware trojan vulnerabilities, prevention and detection / Hassan Salmani.
Author Salmani, Hassan, author.
ISBN 9783319790817 (electronic book)
3319790811 (electronic book)
9783319790800
3319790803
DOI https://doi.org/10.1007/978-3-319-79081-7
Published Cham, Switzerland : Springer, [2018]
Copyright ©2018
Language English
Description 1 online resource
Item Number 10.1007/978-3-319-79081-7 doi
Call Number QA76.9.A25
Dewey Decimal Classification 005.8
Summary This book describes the integrated circuit supply chain flow and discusses security issues across the flow, which can undermine the trustworthiness of final design. The author discusses and analyzes the complexity of the flow, along with vulnerabilities of digital circuits to malicious modifications (i.e. hardware Trojans) at the register-transfer level, gate level and layout level. Various metrics are discussed to quantify circuit vulnerabilities to hardware Trojans at different levels. Readers are introduced to design techniques for preventing hardware Trojan insertion and to facilitate hardware Trojan detection. Trusted testing is also discussed, enabling design trustworthiness at different steps of the integrated circuit design flow. Coverage also includes hardware Trojans in mixed-signal circuits. Provides a comprehensive vulnerability analysis across the integrated circuits design flow; Introduces security metrics to measure quantitatively the vulnerability of a circuit to hardware Trojan insertion; Describes design techniques to prevent hardware Trojan insertion and to facilitate hardware Trojan detection; Presents testing techniques for trustworthiness at each circuit level.
Bibliography, etc. Note Includes bibliographical references.
Access Note Access limited to authorized users.
Digital File Characteristics text file PDF
Source of Description Online resource; title from PDF title page (viewed April 25, 2018).
Available in Other Form Trusted digital circuits.
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Intro; Preface; Contents; 1 The Global Integrated Circuit Supply Chain Flow and the Hardware Trojan Attack; 1.1 The Global Integrated Circuit Supply Chain; 1.2 The Hardware Trojan Attack; 1.3 Conclusions; References; 2 Circuit Vulnerabilities to Hardware Trojans at the Register-Transfer Level; 2.1 Circuits at the Register-Transfer Level; 2.2 Value Range Analyses for Vulnerability Assessments; 2.2.1 Statement Analysis; 2.2.2 Observerability Analysis; 2.2.3 Application of Value Range-Based Vulnerability Analysis; 2.3 Unspecified IP Functionality; 2.3.1 Hardware Trojans in Don't Cares.

2.3.2 Dangerous Don't Cares Identification2.4 Formal Verification and Coverage Analysis for Vulnerability Analyses; 2.5 Conclusions; References; 3 Design Techniques for Hardware Trojans Prevention and Detection at the Register-Transfer Level; 3.1 Hardware Trojan Prevention at the Register-Transfer Level; 3.1.1 Dual Modular Redundant Schedule at High-Level Synthesis; 3.1.2 Proof-Carrying Hardware; 3.2 Hardware Trojan Detection at the Register-Transfer Level; 3.2.1 Control-Flow Subgraph Matching; 3.3 Conclusions; References; 4 Circuit Vulnerabilities to Hardware Trojans at the Gate Level.

4.1 Circuits at the Gate-Level4.2 Analyzing Vulnerabilities Based on Functional Analyses; 4.3 Analyzing Vulnerabilities Based on Structural and Parametric Analyses; 4.3.1 Hardware Trojan Ranking; 4.4 Analyzing Vulnerabilities in Finite State Machines and Design-for-Test Structures; 4.5 Conclusions; References; 5 Design Techniques for Hardware Trojans Prevention and Detection at the Gate Level; 5.1 Hardware Trojan Prevention at the Gate Level; 5.1.1 Information Flow Tracking for Hardware Trojan Prevention; 5.2 Hardware Trojan Detection at the Gate Level.

5.2.1 Signal Correlation-Based Clustering for Hardware Trojan Detection5.2.2 Score-Based Classification for Hardware Trojans Detection; 5.2.3 The Controllability and Observability Hardware Trojan Detection (COTD); 5.2.3.1 Complexity: COTD vs. Some Existing Techniques; 5.2.3.2 Simulation Analyses; 5.3 Conclusions; References; 6 Circuit Vulnerabilities to Hardware Trojan at the Layout Level; 6.1 Circuits at the Layout Level; 6.2 Motivation; 6.3 Layout Vulnerability Analysis Flow; 6.3.1 Cell and Routing Analyses; 6.3.2 Net Analysis; 6.4 Simulation Results; 6.5 Conclusions; References.

7 Design Techniques for Hardware Trojans Prevention and Detection at the Layout Level7.1 Hardware Trojan Prevention at the Layout Level; 7.1.1 Dummy Scan Flip-flop Insertion and Layout-Aware Scan Cell Reordering; 7.1.2 Ring Oscillator Network; 7.1.3 Trojan Prevention and Detection (TPAD) Technique; 7.1.4 Infrastructure IP for Security (IIPS) Technique; 7.2 Hardware Trojan Detection at the Layout Level; 7.2.1 The Current Integration Technique; 7.2.2 Delay-Based Hardware Trojan Detection Using Shadow Registers; 7.2.3 Temperature-Based Hardware Trojan Detection.

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