000839580 000__ 08177cam\a2200601Mi\4500
000839580 001__ 839580
000839580 005__ 20230306144737.0
000839580 006__ m\\\\\o\\d\\\\\\\\
000839580 007__ cr\un\nnnunnun
000839580 008__ 180407s2018\\\\gw\\\\\\o\\\\\000\0\eng\d
000839580 019__ $$a1033602368$$a1034542347$$a1041479605$$a1041671756
000839580 020__ $$a9783319788906
000839580 020__ $$a3319788906
000839580 020__ $$z9783319788890
000839580 020__ $$a3319788892
000839580 020__ $$a9783319788890
000839580 0247_ $$a10.1007/978-3-319-78890-6$$2doi
000839580 035__ $$aSP(OCoLC)on1038410537
000839580 035__ $$aSP(OCoLC)1038410537$$z(OCoLC)1033602368$$z(OCoLC)1034542347$$z(OCoLC)1041479605$$z(OCoLC)1041671756
000839580 040__ $$aUPM$$beng$$cUPM$$dOCLCO$$dGW5XE$$dAZU$$dUWO$$dCOO$$dUAB$$dOCLCF$$dOCLCQ
000839580 049__ $$aISEA
000839580 050_4 $$aQA75.5-76.95
000839580 050_4 $$aTK7885-7895
000839580 08204 $$a004$$223
000839580 24500 $$aApplied Reconfigurable Computing. Architectures, Tools, and Applications :$$b14th International Symposium, ARC 2018, Santorini, Greece, May 2-4, 2018, Proceedings /$$cedited by Nikolaos Voros, Michael Huebner, Georgios Keramidas, Diana Goehringer, Christos Antonopoulos, Pedro C. Diniz.
000839580 264_1 $$aCham :$$bSpringer International Publishing :$$bImprint: Springer,$$c2018.
000839580 300__ $$a1 online resource (xvi, 753 pages) :$$billustrations.
000839580 336__ $$atext$$btxt$$2rdacontent
000839580 337__ $$acomputer$$bc$$2rdamedia
000839580 338__ $$aonline resource$$bcr$$2rdacarrier
000839580 347__ $$atext file$$bPDF$$2rda
000839580 4901_ $$aLecture Notes in Computer Science,$$x0302-9743 ;$$v10824
000839580 5050_ $$aMachine Learning and Neural Networks -- Approximate FPGA-based LSTMs under Computation Time Constraints -- Redundancy-reduced MobileNet Acceleration on Reconfigurable Logic For ImageNet Classification -- Accuracy to Throughput Trade-offs for Reduced Precision Neural Networks on Reconfigurable Logic -- Deep Learning on High Performance FPGA Switching Boards: Flow-in-Cloud -- SqueezeJet: High-level Synthesis Accelerator Design for Deep Convolutional Neural Networks -- Efficient hardware acceleration of recommendation engines: a use case on collaborative filtering -- FPGA-based Design and CGRA Optimizations -- VerCoLib: Fast and Versatile Communication for FPGAs via PCI Express -- Performance Estimation of FPGA Modules for Modular Design Methodology using Artificial Neural Network -- Achieving Efficient Realization of Kalman Filter on CGRA through Algorithm-Architecture Co-design -- FPGA-based Memory Efficient Shift-And Algorithm for Regular Expression Matching -- Towards an optimized multi FPGA architecture with STDM network: a preliminary study -- Applications and Surveys -- An FPGA/HMC-based Accelerator for Resolution Proof Checking -- An Efficient FPGA Implementation of the Big Bang-Big Crunch Optimization Algorithm -- ReneGENE-GI: Empowering Precision Genomics with FPGAs on HPCs.-FPGA-based Parallel Pattern Matching -- Embedded Vision Systems: A Review of the Literature -- A Survey of Low Power Design Techniques for Last Level Caches -- Fault-Tolerance, Security and Communication Architectures -- ISA-DTMR: Selective Protection in Configurable Heterogeneous Multicores -- Analyzing AXI Streaming Interface for Hardware Acceleration in AP-SoC under Soft Errors -- High Performance UDP/IP 40Gb Ethernet Stack for FPGAs -- Tackling Wireless Sensor Network Heterogeneity Through Novel Reconfigurable Gateway Approach -- A Low-Power FPGA-Based Architecture for Microphone Arrays in Wireless Sensor Networks -- A Hybrid FPGA Trojan Detection Technique Based-on Combinatorial Testing and On-chip Sensing -- HoneyWiN: Novel Honeycomb-based Wireless NoC Architecture in Many-Core Era -- Reconfigurable and Adaptive Architectures -- Fast Partial Reconfiguration on SRAM-based FPGAs: A Frame-Driven Routing Approach -- A Dynamic Partial Reconfigurable Overlay Framework for Python -- Runtime Adaptive Cache for the LEON3 Processor -- Exploiting Partial Reconfiguration on a Dynamic Coarse Grained Reconfigurable Architecture -- DIM-VEX: Exploiting Design Time Configurability and Runtime Reconfigurability -- The use of HACP+SBT lossless compression in optimizing memory bandwidth requirement for hardware implementation of background modelling algorithms -- A Reconfigurable PID Controller -- Design Methods and Fast Prototyping -- High-Level Synthesis of Software-defined MPSoCs -- Improved High-Level Synthesis for Complex CellML Models -- An Intrusive Dynamic Reconfigurable Cycle-accurate Debugging System for Embedded Processors -- Rapid prototyping and verification of hardware modules generated using HLS -- Comparing C and SystemC Based HLS Methods for Reconfigurable Systems Design -- Fast DSE for Automated Parallelization of Embedded Legacy Applications -- Control Flow Analysis for Embedded Multi-Core Hybrid Systems -- FPGA-based Design and Applications -- A Low-Cost BRAM-based Function Reuse for Configurable Soft-Core Processors in FPGAs -- A Parallel-Pipelined OFDM Baseband Modulator with Dynamic Frequency Scaling for 5G Systems -- Area-Energy Aware Dataow Optimisation of Visual Tracking Systems -- Fast Carry Chain based Architectures for Two's Complement to CSD Recoding on FPGAs -- Exploring Functional Acceleration of OpenCL on FPGAs and GPUs Through Platform-Independent Optimizations -- ReneGENE-Novo: Co-designed Algorithm-Architecture for Accelerated Preprocessing and Assembly of Genomic Short Reads -- An OpenCL Implementation of WebP Accelerator on FPGAs -- Efficient Multitasking on FPGA Using HDL-based Checkpointing -- High Level Synthesis Implementation of Object Tracking Algorithm on Reconfigurable Hardware -- Reconfigurable FPGA-Based Channelization Using Polyphase Filter Banks for Quantum Computing Systems -- Reconfigurable IP-Based Spectral Interference Canceller -- FPGA-Assisted Distribution Grid Simulator -- Analyzing the Use of Taylor Series Approximation in Hardware and Embedded Software for Good Cost-Accuracy Tradeoffs -- Special Session: Research Projects -- CGRA Tool Flow for Fast Run-Time Reconfiguration -- Seamless FPGA deployment over Spark in cloud computing: A use case on Machine learning hardware acceleration -- The ARAMiS Project Initiative: Multicore Systems in Safety- and Mixed-Critical Applications -- Mapping and scheduling hard real time applications on multicore systems -- The ARGO approach -- Robots in assisted living environments as an unobtrusive, efficient, reliable and modular solution for independent ageing: The RADIO Experience -- HLS Algorithmic Explorations for HPC Execution on Reconfigurable Hardware ECOSCALE -- Supporting uTilities for Heterogeneous EMbedded image processing platforms (STHEM): An Overview.
000839580 506__ $$aAccess limited to authorized users.
000839580 520__ $$aThis book constitutes the proceedings of the 14th International Conference on Applied Reconfigurable Computing, ARC 2018, held in Santorini, Greece, in May 2018. The 29 full papers and 22 short presented in this volume were carefully reviewed and selected from 78 submissions. In addition, the volume contains 9 contributions from research projects. The papers were organized in topical sections named: machine learning and neural networks; FPGA-based design and CGRA optimizations; applications and surveys; fault-tolerance, security and communication architectures; reconfigurable and adaptive architectures; design methods and fast prototyping; FPGA-based design and applications; and special session: research projects. .
000839580 650_0 $$aComputer science.
000839580 650_0 $$aComputer hardware.
000839580 650_0 $$aComputer organization.
000839580 650_0 $$aSoftware engineering.
000839580 650_0 $$aArtificial intelligence.
000839580 650_0 $$aImage processing.
000839580 7001_ $$aVoros, Nikolaos.$$eeditor.
000839580 7001_ $$aHuebner, Michael.$$eeditor.
000839580 7001_ $$aKeramidas, Georgios.$$eeditor.
000839580 7001_ $$aGoehringer, Diana.$$eeditor.
000839580 7001_ $$aAntonopoulos, Christos.$$eeditor.
000839580 7001_ $$aDiniz, Pedro C.$$eeditor.
000839580 77608 $$iPrint version: $$z9783319788890
000839580 830_0 $$aLecture notes in computer science ;$$v10824.
000839580 852__ $$bebk
000839580 85640 $$3SpringerLink$$uhttps://univsouthin.idm.oclc.org/login?url=http://link.springer.com/10.1007/978-3-319-78890-6$$zOnline Access$$91397441.1
000839580 909CO $$ooai:library.usi.edu:839580$$pGLOBAL_SET
000839580 980__ $$aEBOOK
000839580 980__ $$aBIB
000839580 982__ $$aEbook
000839580 983__ $$aOnline
000839580 994__ $$a92$$bISE