TY  - GEN
N2  - Quantitative understanding of the parasitic capacitances and inductances and the resultant propagation delays and crosstalk phenomena associated with the metallic interconnections on the very large scale integrated (VLSI) circuits has become extremely important for the optimum design of the state-of-the-art integrated circuits. It is because more than 65 percent of the delays on the integrated circuit chip occur in the interconnections and not in the transistors on the chip. Mathematical techniques to model the parasitic capacitances, inductances, propagation delays, crosstalk noise, and electromigration-induced failure associated with the interconnections in the realistic high-density environment on a chip will be discussed. An overview of the future interconnection technologies for the nanotechnology circuits will also be presented. This book will be the first book of its kind written for a one-semester course on the mathematical modeling of metallic interconnections on a VLSI circuit. In most institutions around the world offering BS, MS, and Ph.D. degrees in Electrical and Computer Engineering, such a course will be suitable for the first-year graduate students and it will also be appropriate as an elective course for senior level BS students. This book will also be of interest to practicing engineers in the field who are looking for a quick refresher on this subject.
DO  - doi
AB  - Quantitative understanding of the parasitic capacitances and inductances and the resultant propagation delays and crosstalk phenomena associated with the metallic interconnections on the very large scale integrated (VLSI) circuits has become extremely important for the optimum design of the state-of-the-art integrated circuits. It is because more than 65 percent of the delays on the integrated circuit chip occur in the interconnections and not in the transistors on the chip. Mathematical techniques to model the parasitic capacitances, inductances, propagation delays, crosstalk noise, and electromigration-induced failure associated with the interconnections in the realistic high-density environment on a chip will be discussed. An overview of the future interconnection technologies for the nanotechnology circuits will also be presented. This book will be the first book of its kind written for a one-semester course on the mathematical modeling of metallic interconnections on a VLSI circuit. In most institutions around the world offering BS, MS, and Ph.D. degrees in Electrical and Computer Engineering, such a course will be suitable for the first-year graduate students and it will also be appropriate as an elective course for senior level BS students. This book will also be of interest to practicing engineers in the field who are looking for a quick refresher on this subject.
T1  - A one-semester course in modeling of VLSI interconnections /
AU  - Goel, Ashok K.,
CN  - TK7874.75
ID  - 841654
KW  - Integrated circuits
KW  - VLSI
KW  - Integrated Circuits
KW  - Interconnections
KW  - Copper Interconnections
KW  - Propagation Delays
KW  - Crosstalk
KW  - Modeling
KW  - Electromigration
KW  - Capacitances
KW  - Inductances
KW  - Nanotechnology
SN  - 9781606505137
TI  - A one-semester course in modeling of VLSI interconnections /
LK  - https://univsouthin.idm.oclc.org/login?url=https://ebookcentral.proquest.com/lib/usiricelib-ebooks/detail.action?docID=1911666
UR  - https://univsouthin.idm.oclc.org/login?url=https://ebookcentral.proquest.com/lib/usiricelib-ebooks/detail.action?docID=1911666
ER  -