Advanced HDL Synthesis and SOC Prototyping : RTL Design Using Verilog / Vaibbhav Taraate.
2019
TK7895.E42
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Details
Title
Advanced HDL Synthesis and SOC Prototyping : RTL Design Using Verilog / Vaibbhav Taraate.
Author
ISBN
9789811087769 (electronic book)
9811087768 (electronic book)
9789811087752
981108775X
9811087768 (electronic book)
9789811087752
981108775X
Publication Details
Singapore : Springer, c2019.
Language
English
Description
1 online resource (319 pages)
Call Number
TK7895.E42
Dewey Decimal Classification
621.3815
Access Note
Access limited to authorized users.
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Description based on print version record.
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