TY  - GEN
AU  - Rajaram, S.,
AU  - Balamurugan, N. B.
AU  - Gracia Nirmala Rani, D.
AU  - Singh, Virendra
CN  - TK7874.75
DO  - 10.1007/978-981-13-5950-7
DO  - doi
ID  - 862672
KW  - Integrated circuits
KW  - Integrated circuits
LK  - https://univsouthin.idm.oclc.org/login?url=http://link.springer.com/10.1007/978-981-13-5950-7
N1  - Includes author index.
SN  - 9789811359507
SN  - 9811359504
T1  - VLSI design and test :22nd International Symposium, VDAT 2018, Madurai, India, June 28-30, 2018, Revised selected papers /
TI  - VLSI design and test :22nd International Symposium, VDAT 2018, Madurai, India, June 28-30, 2018, Revised selected papers /
UR  - https://univsouthin.idm.oclc.org/login?url=http://link.springer.com/10.1007/978-981-13-5950-7
VL  - 892
ER  -