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000862909 020__ $$a9783030109585$$q(electronic book)
000862909 020__ $$a3030109585$$q(electronic book)
000862909 020__ $$z9783030109578
000862909 020__ $$a3030109577
000862909 020__ $$a9783030109578
000862909 0247_ $$a10.1007/978-3-030-10958-5$$2doi
000862909 035__ $$aSP(OCoLC)on1084655082
000862909 035__ $$aSP(OCoLC)1084655082
000862909 040__ $$aGW5XE$$beng$$erda$$epn$$cGW5XE$$dEBLCP$$dUAB$$dUKMGB$$dVT2$$dOCLCF
000862909 049__ $$aISEA
000862909 050_4 $$aTK7872.P38
000862909 08204 $$a621.3815/364$$223
000862909 1001_ $$aMarkulic, Nereo,$$eauthor.
000862909 24510 $$aDigital subsampling phase lock techniques for frequency synthesis and polar transmission /$$cNereo Markulic, Kuba Raczkowski, Jan Craninckx, Piet Wambacq.
000862909 264_1 $$aCham, Switzerland :$$bSpringer,$$c2019.
000862909 300__ $$a1 online resource (xxiii, 138 pages) :$$billustrations.
000862909 336__ $$atext$$btxt$$2rdacontent
000862909 337__ $$acomputer$$bc$$2rdamedia
000862909 338__ $$aonline resource$$bcr$$2rdacarrier
000862909 4901_ $$aAnalog circuits and signal processing,$$x1872-082X
000862909 504__ $$aIncludes bibliographical references and index.
000862909 506__ $$aAccess limited to authorized users.
000862909 588__ $$aOnline resource; title from PDF title page (SpringerLink, viewed February 6, 2019).
000862909 650_0 $$aPhase-locked loops.
000862909 650_0 $$aIntegrated circuits.
000862909 7001_ $$aRaczkowski, Kuba,$$eauthor.
000862909 7001_ $$aCraninckx, J.$$q(Jan),$$eauthor.
000862909 7001_ $$aWambacq, Piet,$$eauthor.
000862909 830_0 $$aAnalog circuits and signal processing series.
000862909 852__ $$bebk
000862909 85640 $$3SpringerLink$$uhttps://univsouthin.idm.oclc.org/login?url=http://link.springer.com/10.1007/978-3-030-10958-5$$zOnline Access$$91397441.1
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