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000898601 020__ $$a9783030234256$$q(electronic book)
000898601 020__ $$a3030234258$$q(electronic book)
000898601 020__ $$z9783030234249
000898601 0248_ $$a10.1007/978-3-030-23
000898601 035__ $$aSP(OCoLC)on1106169565
000898601 035__ $$aSP(OCoLC)1106169565
000898601 040__ $$aLQU$$beng$$erda$$cLQU$$dNOC$$dGW5XE$$dOCLCF$$dYDXIT$$dUKMGB$$dDKU
000898601 049__ $$aISEA
000898601 050_4 $$aTK7874.75$$b.I34 2018
000898601 08204 $$a004.6$$223
000898601 1112_ $$aIEEE/IFIP International Conference on VLSI and System-on-Chip$$n(26th :$$d2018 :$$cVerona, Italy)
000898601 24510 $$aVLSI-SoC :$$bdesign and engineering of electronics systems based on new computing paradigms : 26th IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2018, Verona, Italy, October 8-10, 2018, Revised and extended selected papers /$$cNicola Bombieri, Graziano Pravadelli, Masahiro Fujita, Todd Austin, Ricardo Reis (Eds.).
000898601 2463_ $$aVLSI-SoC 2018
000898601 264_1 $$aCham, Switzerland :$$bSpringer,$$c[2019]
000898601 300__ $$a1 online resource
000898601 336__ $$atext$$btxt$$2rdacontent
000898601 337__ $$acomputer$$bc$$2rdamedia
000898601 338__ $$aonline resource$$bcr$$2rdacarrier
000898601 4901_ $$aIFIP advances in information and communication technology ;$$v561
000898601 500__ $$aIncludes author index.
000898601 50580 $$tA 58 nm CMOS synthesizable digital low-dropout regulator based on voltage-to-time conversion with 99.6% current efficiency at 10-mA load /$$rNaoki Ojima, Toru Nakura, Tetsuya Iizuka, and Kunihiro Asada --$$tAn instruction set architecture for secure, low-power, dynamic IoT communication /$$rShahzad Muzaffar and Ibrahim (Abe) M. Elfadel --$$tThe connection layout in a lattice of four-terminal switches /$$rAnna Bernasconi, Antonio Boffa, Fabrizio Luccio, and Linda Pagli --$$tBuilding high-performance, easy-to-use polymorphic parallel memories with HLS /$$rL. Stornaiuolo, M. Rabozzi, M. D. Santambrogio, D. Sciuto, C. B. Ciobanu, G. Stramondo, and A. L. Varbanescu --$$tRectification of arithmetic circuits with Craig interpolants in finite fields /$$rUtkarsh Gupta, Irina Ilioaea, Vikas Rao, Arpitha Srinath, Priyank Kalla, and Florian Enescu --$$tEnergy-accuracy scalable deep convolutional neural networks : a Pareto analysis /$$rValentino Peluso and Andrea Calimera --$$tReRAM based in-memory computation of single bit error correcting BCH code /$$rSwagata Mandal, Yaswanth Tavva, Debjyoti Bhattacharjee, and Anupam Chattopadhyay --$$tOptimizing performance and energy overheads due to fanout in in-memory computing systems /$$rMd Adnan Zaman, Rajeev Joshi, and Srinivas Katkoori --$$tMapping spiking neural networks on multi-core neuromorphic platforms : problem formulation and performance analysis /$$rFrancesco Barchi, Gianvito Urgese, Enrico Macii, and Andrea Acquaviva --$$tImproved test solutions for COTS-based systems in space applications /$$rRiccardo Cantoro, Sara Carbonara, Andrea Floridia, Ernesto Sanchez, Matteo Sonza Reorda, and Jan-Gerd Mess
000898601 50580 $$tAnalysis of bridge defects in STT-MRAM cells under process variations and a robust DFT technique for their detection /$$rVictor Champac, Andres Gomez, Freddy Forero, and Kaushik Roy --$$tAssessment of low-budget targeted cyberattacks against power systems /$$rXiaoRui Liu, Anastasis Keliris, Charalambos Konstantinou, Marios Sazos, and Michail Maniatakos --$$tEfficient hardware/software co-design for NTRU /$$rTim Fritzmann, Thomas Schamberger, Christoph Frisch, Konstantin Braun, Georg Maringer, and Johanna Sepúlveda --$$tCorrection to: Improved test solutions for COTS-based systems in space applications /$$rRiccardo Cantoro, Sara Carbonara, Andrea Floridia, Ernesto Sanchez, Matteo Sonza Reorda, and Jan-Gerd Mess.
000898601 506__ $$aAccess limited to authorized users.
000898601 520__ $$aThis book contains extended and revised versions of the best papers presented at the 26th IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2018, held in Verona, Italy, in October 2018. The 13 full papers included in this volume were carefully reviewed and selected from the 27 papers (out of 106 submissions) presented at the conference. The papers discuss the latest academic and industrial results and developments as well as future trends in the field of System-on-Chip (SoC) design, considering the challenges of nano-scale, state-of-the-art and emerging manufacturing technologies. In particular they address cutting-edge research fields like heterogeneous, neuromorphic and brain-inspired, biologically-inspired, approximate computing systems.
000898601 588__ $$aDescription based on online resource; title from digital title page (viewed on August 12, 2019).
000898601 650_0 $$aIntegrated circuits$$xVery large scale integration$$vCongresses.
000898601 650_0 $$aSystems on a chip$$vCongresses.
000898601 650_0 $$aComputer network architectures$$vCongresses.
000898601 650_0 $$aInternet of things$$vCongresses.
000898601 7001_ $$aBombieri, Nicola,$$eeditor.
000898601 7001_ $$aPravadelli, Graziano,$$eeditor.
000898601 7001_ $$aFujita, Masahiro,$$eeditor.
000898601 7001_ $$aAustin, Todd,$$eeditor.
000898601 7001_ $$aReis, Ricardo A. L.$$q(Ricardo Augusto da Luz),$$eeditor.
000898601 830_0 $$aIFIP advances in information and communication technology ;$$v561.
000898601 852__ $$bebk
000898601 85640 $$3SpringerLink$$uhttps://univsouthin.idm.oclc.org/login?url=http://link.springer.com/10.1007/978-3-030-23425-6$$zOnline Access$$91397441.1
000898601 909CO $$ooai:library.usi.edu:898601$$pGLOBAL_SET
000898601 980__ $$aEBOOK
000898601 980__ $$aBIB
000898601 982__ $$aEbook
000898601 983__ $$aOnline
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