TY  - GEN
AU  - Sengupta, Anirban,
AU  - Dasgupta, Sudeb,
AU  - Singh, Virendra
AU  - Sharma, Rohit
AU  - Vishvakarma, Santosh Kumar,
CN  - TK7874.75
DO  - 10.1007/978-981-32-9767-8
DO  - doi
ID  - 913576
KW  - Integrated circuits
KW  - Integrated circuits
LK  - https://univsouthin.idm.oclc.org/login?url=http://link.springer.com/10.1007/978-981-32-9767-8
N1  - Includes author index.
SN  - 9789813297678
SN  - 9813297670
T1  - VLSI design and test :23rd International Symposium, VDAT 2019, Indore, India, July 4-6, 2019, Revised selected papers /
TI  - VLSI design and test :23rd International Symposium, VDAT 2019, Indore, India, July 4-6, 2019, Revised selected papers /
UR  - https://univsouthin.idm.oclc.org/login?url=http://link.springer.com/10.1007/978-981-32-9767-8
VL  - 1066
ER  -