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000922961 019__ $$a1125992938
000922961 020__ $$a9783030247379$$q(electronic book)
000922961 020__ $$a3030247376$$q(electronic book)
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000922961 0247_ $$a10.1007/978-3-030-24737-9$$2doi
000922961 0247_ $$a10.1007/978-3-030-24
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000922961 050_4 $$aTK7885.7$$b.M44 2020eb
000922961 08204 $$a621.39/2$$223
000922961 1001_ $$aMehta, Ashok B.,$$eauthor.
000922961 24510 $$aSystem Verilog assertions and functional coverage :$$bguide to language, methodology and applications /$$cAshok B. Mehta.
000922961 250__ $$aThird edition.
000922961 264_1 $$aCham :$$bSpringer,$$c[2020]
000922961 264_4 $$c©2020
000922961 300__ $$a1 online resource :$$billustrations
000922961 336__ $$atext$$btxt$$2rdacontent
000922961 337__ $$acomputer$$bc$$2rdamedia
000922961 338__ $$aonline resource$$bcr$$2rdacarrier
000922961 500__ $$aIncludes index.
000922961 506__ $$aAccess limited to authorized users.
000922961 520__ $$aThis book provides a hands-on, application-oriented guide to the language and methodology of both SystemVerilog Assertions and Functional Coverage. Readers will benefit from the step-by-step approach to learning language and methodology nuances of both SystemVerilog Assertions and Functional Coverage, which will enable them to uncover hidden and hard to find bugs, point directly to the source of the bug, provide for a clean and easy way to model complex timing checks and objectively answer the question 'have we functionally verified everything. Written by a professional end-user of ASIC/SoC/CPU and FPGA design and Verification, this book explains each concept with easy to understand examples, simulation logs and applications derived from real projects. Readers will be empowered to tackle the modeling of complex checkers for functional verification and exhaustive coverage models for functional coverage, thereby drastically reducing their time to design, debug and cover. This updated third edition addresses the latest functional set released in IEEE-1800 (2012) LRM, including numerous additional operators and features. Additionally, many of the Concurrent Assertions/Operators explanations are enhanced, with the addition of more examples and figures. · Covers in its entirety the latest IEEE-1800 2012 LRM syntax and semantics; · Covers both SystemVerilog Assertions and SystemVerilog Functional Coverage languages and methodologies; · Provides practical applications of the what, how and why of Assertion Based Verification and Functional Coverage methodologies; · Explains each concept in a step-by-step fashion and applies it to a practical real life example; · Includes 6 practical LABs that enable readers to put in practice the concepts explained in the book.
000922961 588__ $$aOnline resource; title from PDF title page (SpringerLink, viewed October 15, 2019).
000922961 650_0 $$aVerilog (Computer hardware description language)
000922961 650_0 $$aElectronic digital computers$$xDesign and construction.
000922961 650_0 $$aIntegrated circuits$$xVerification.
000922961 852__ $$bebk
000922961 85640 $$3SpringerLink$$uhttps://univsouthin.idm.oclc.org/login?url=http://link.springer.com/10.1007/978-3-030-24737-9$$zOnline Access$$91397441.1
000922961 909CO $$ooai:library.usi.edu:922961$$pGLOBAL_SET
000922961 980__ $$aEBOOK
000922961 980__ $$aBIB
000922961 982__ $$aEbook
000922961 983__ $$aOnline
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