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000923628 020__ $$a9783030305963$$q(electronic book)
000923628 020__ $$a3030305961$$q(electronic book)
000923628 0247_ $$a10.1007/978-3-030-30$$2doi
000923628 035__ $$aSP(OCoLC)on1129170969
000923628 035__ $$aSP(OCoLC)1129170969
000923628 040__ $$aLQU$$beng$$cLQU$$dGW5XE$$dN$T
000923628 049__ $$aISEA
000923628 050_4 $$aTK7895.E42
000923628 08204 $$a006.2/2$$223
000923628 1001_ $$aFarahmandi, Farimah,$$eauthor.
000923628 24510 $$aSystem-on-chip security :$$bvalidation and verification /$$cFarimah Farahmandi, Yuanwen Huang, Prabhat Mishra.
000923628 264_1 $$aCham, Switzerland :$$bSpringer,$$c[2020]
000923628 300__ $$a1 online resource (xix, 289 pages) :$$billustrations.
000923628 336__ $$atext$$btxt$$2rdacontent
000923628 337__ $$acomputer$$bc$$2rdamedia
000923628 338__ $$aonline resource$$bcr$$2rdacarrier
000923628 504__ $$aIncludes bibliographical references and index.
000923628 5050_ $$aIntroduction -- Security Verification Using Formal Methods -- Simulation-Based Security Validation Approaches -- Security Validation Using Side-Channel Analysis -- Automated Vulnerability Detection And Mitigation -- Conclusion.
000923628 506__ $$aAccess limited to authorized users.
000923628 520__ $$aThis book describes a wide variety of System-on-Chip (SoC) security threats and vulnerabilities, as well as their sources, in each stage of a design life cycle. The authors discuss a wide variety of state-of-the-art security verification and validation approaches such as formal methods and side-channel analysis, as well as simulation-based security and trust validation approaches. This book provides a comprehensive reference for system on chip designers and verification and validation engineers interested in verifying security and trust of heterogeneous SoCs. Outlines a wide variety of hardware security threats and vulnerabilities as well as their sources in each of the stages of a design life cycle; Summarizes unsafe current design practices that lead to security and trust vulnerabilities; Covers state-of-the-art techniques as well as ongoing research efforts in developing scalable security validation using formal methods including symbolic algebra, model checkers, SAT solvers, and theorem provers; Explains how to leverage security validation approaches to prevent side-channel attacks; Presents automated debugging and patching techniques in the presence of security vulnerabilities; Includes case studies for security validation of arithmetic circuits, controller designs, as well as processor-based SoCs.
000923628 588__ $$aOnline resource; title from PDF title page (SpringerLink, viewed December 2, 2019).
000923628 650_0 $$aSystems on a chip$$xSecurity measures.
000923628 650_0 $$aSystems on a chip$$xDesign.
000923628 7001_ $$aHuang, Yuanwen,$$eauthor.
000923628 7001_ $$aMishra, Prabhat,$$d1973-$$eauthor.
000923628 852__ $$bebk
000923628 85640 $$3SpringerLink$$uhttps://univsouthin.idm.oclc.org/login?url=http://link.springer.com/10.1007/978-3-030-30596-3$$zOnline Access$$91397441.1
000923628 909CO $$ooai:library.usi.edu:923628$$pGLOBAL_SET
000923628 980__ $$aEBOOK
000923628 980__ $$aBIB
000923628 982__ $$aEbook
000923628 983__ $$aOnline
000923628 994__ $$a92$$bISE