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000923702 020__ $$a9789811509827$$q(electronic book)
000923702 020__ $$a9811509824$$q(electronic book)
000923702 020__ $$z9789811509810
000923702 0248_ $$a10.1007/978-981-15-0
000923702 035__ $$aSP(OCoLC)on1129218064
000923702 035__ $$aSP(OCoLC)1129218064
000923702 040__ $$aLQU$$beng$$cLQU$$dGW5XE$$dOCLCF
000923702 049__ $$aISEA
000923702 050_4 $$aTK7871.99.M44
000923702 08204 $$a004.6
000923702 1001_ $$aGupta, Kirti.
000923702 24510 $$aModel and Design of Improved Current Mode Logic Gates :$$bDifferential and Single-ended /$$cby Kirti Gupta, Neeta Pandey, Maneesha Gupta.
000923702 264_1 $$aSingapore :$$bSpringer,$$c2020.
000923702 300__ $$a1 online resource (xiv, 171 pages) :$$billustrations.
000923702 336__ $$atext$$btxt$$2rdacontent
000923702 337__ $$acomputer$$bc$$2rdamedia
000923702 338__ $$aonline resource$$bcr$$2rdacarrier
000923702 504__ $$aIncludes bibliographical references.
000923702 5050_ $$aIntroduction -- Current Mode Logic (CML): Basic concepts -- Differential CML Gates with Modified PDN -- CML Gates with Modified Current Source -- CML Gates with Modified Load -- PFSCL Circuits with Reduced Gate Count -- Tri-State CML Circuits.
000923702 506__ $$aAccess limited to authorized users.
000923702 520__ $$aThis book presents MOSFET-based current mode logic (CML) topologies, which increase the speed, and lower the transistor count, supply voltage and power consumption. The improved topologies modify the conventional PDN, load, and the current source sections of the basic CML gates. Electronic system implementation involves embedding digital and analog circuits on a single die shifting towards mixed-mode circuit design. The high-resolution, low-power and low-voltage analog circuits are combined with high-frequency complex digital circuits, and the conventional static CMOS logic generates large current spikes during the switching (also referred to as digital switching noise), which degrade the resolution of the sensitive analog circuits via supply line and substrate coupling. This problem is exacerbated further with scaling down of CMOS technology due to higher integration levels and operating frequencies. In the literature, several methods are described to reduce the propagation of the digital switching noise. However, in high-resolution applications, these methods are not sufficient. The conventional CMOS static logic is no longer an effective solution, and therefore an alternative with reduced current spikes or that draws a constant supply current must be selected. The current mode logic (CML) topology, with its unique property of requiring constant supply current, is a promising alternative to the conventional CMOS static logic.
000923702 650_0 $$aMetal oxide semiconductor field-effect transistors.
000923702 650_0 $$aLogic circuits.
000923702 7001_ $$aPandey, Neeta.
000923702 7001_ $$aGupta, Maneesha.
000923702 852__ $$bebk
000923702 85640 $$3SpringerLink$$uhttps://univsouthin.idm.oclc.org/login?url=http://link.springer.com/10.1007/978-981-15-0982-7$$zOnline Access$$91397441.1
000923702 909CO $$ooai:library.usi.edu:923702$$pGLOBAL_SET
000923702 980__ $$aEBOOK
000923702 980__ $$aBIB
000923702 982__ $$aEbook
000923702 983__ $$aOnline
000923702 994__ $$a92$$bISE