Logic synthesis and SOC prototyping : RTL design using VHDL / Vaibbhav Taraate.

Unlimited

Authorized users

Can lend chapters, not whole ebooks

Logic synthesis and SOC prototyping : RTL design using VHDL / Vaibbhav Taraate.

9789811513145 (electronic book)
9811513147 (electronic book)
9789811513138
9811513139

Singapore : Springer, 2020.

English

1 online resource (260 pages)

TK7895.E42

621.3815

This book describes RTL design, synthesis, and timing closure strategies for SOC blocks. It covers high-level RTL design scenarios and challenges for SOC design. The book gives practical information on the issues in SOC and ASIC prototyping using modern high-density FPGAs. The book covers SOC performance improvement techniques, testing, and system-level verification. The book also describes the modern Xilinx FPGA architecture and their use in SOC prototyping. The book covers the Synopsys DC, PT commands, and use of them to constraint and to optimize SOC design. The contents of this book will be of use to students, professionals, and hobbyists alike.

Includes bibliographical references and index.

Access limited to authorized users.

Description based on print version record.

Online Resources > Ebooks
All Resources