Part I Introduction
1 Introduction to 3D Technologies
1.1 Motivation for Heterogenous 3D ICs
1.2 3D Technologies
1.3 TSV CapacitancesA Problem Resistant to Scaling
1.4 Conclusion
2 Interconnect Architectures for 3D Technologies
2.1 Interconnect Architectures
2.2 Overview of Interconnect Architectures for 3D ICs
2.3 Three-dimensional Networks on chips
2.4 Conclusion
Part II 3D Technology Modeling
3 Power and Performance Formulas
3.1 High-Level Formula for the Power Consumption
3.2 High-Level Formula for the Propagation Delay
3.3 Matrix Formulations
3.4 Evaluation
3.5 Conclusion
4 Capacitance Estimation
4.1 Existing Capacitance Models
4.2 Edge and MOS Effects on the TSV Capacitances
4.3 TSV Capacitance Model
4.4 Evaluation
4.5 Conclusion
Part III System Modeling
xiii
xiv Contents
5 Application and Simulation Models
5.1 Overview of the Modeling Approach
5.2 Application Traffic Model
5.3 Simulation Model of 3D NoCs
5.4 Simulator Interfaces
5.5 Conclusion
6 Bit-level Statistics
6.1 Existing Approaches to Estimate the Bit-Level Statistics for
Single Data Streams
6.2 Data-Stream Multiplexing
6.3 Bit-Level Statistics with Data-Stream Multiplexing
6.4 Evaluation
6.5 Conclusion
7 Ratatoskr Framework
7.1 Ratatoskr for Practitioners
7.2 Implementation
7.3 Evaluation
7.4 Case Study: Link Power Estimation and Optimization
7.5 Conclusion
Part IV 3D-Interconnect Optimization
8 Low-Power Technique for 3D Interconnects
8.1 Fundamental Idea
8.2 Power-Optimal TSV assignment
8.3 Systematic Net-to-TSV Assignments
8.4 Combination with Traditional Low-Power Codes
8.5 Evaluation
8.6 Conclusion
9 Low-Power Technique for High-Performance 3D
Interconnects.
9.1 Edge-Effect-Aware Crosstalk Classification
9.2 Existing Approaches and Their Limitations
9.3 Proposed Technique
9.4 Extension to a Low-Power 3D CAC
9.5 Evaluation
9.6 Conclusion
10 Low-Power Technique for High-Performance 3D
Interconnects (Misaligned)
10.1 Temporal-Misalignment Effect on the Crosstalk
10.2 Exploiting Misalignment to Improve the Performance
10.3 Effect on the TSV Power Consumption
Contents xv
10.4 Evaluation
10.5 Conclusion
11 Low-Power Technique for Yield-Enhanced 3D Interconnects
11.1 Existing TSV Yield-Enhancement Techniques
11.2 PreliminariesLogical Impact of TSV Faults
11.3 Fundamental Idea
11.4 Formal Problem Description
11.5 TSV Redundancy Schemes
11.6 Evaluation
11.7 Case Study
11.8 Conclusion
Part V NoC Optimization for Heterogeneous 3D Integration
12 Heterogeneous Buffering for 3D NoCs251
12.1 Buffer Distributions and Depths
12.2 Routers with Optimized Buffer Distribution
12.3 Routers with Optimized Buffer Depths
12.4 Evaluation
12.5 Discussion
12.6 Conclusion
13 Heterogeneous Routing for 3D NoCs
13.1 Heterogeneity and Routing
13.2 Modeling Heterogeneous Technologies
13.3 Modeling Communication
13.4 Routing Limitations from Heterogeneity
13.5 Heterogeneous Routing Algorithms
13.6 Heterogeneous Router Architectures
13.7 Low-Power Routing in Heterogeneous 3D ICs
13.8 Evaluation
13.9 Discussion
13.10Conclusion
14 Heterogeneous Virtualisation for 3D NoCs
14.1 Problem Description
14.2 Heterogeneous Microarchitectures Exploiting Traffic Imbalance
14.3 Evaluation
14.4 Conclusion
15 Network Synthesis and SoC Floor Planning
15.1 Fundamental Idea
15.2 Modelling and Optimization
15.3 Mixed-Integer Linear Program
15.4 Heuristic Solution
xvi Contents
15.5 Evaluation
15.6 Conclusion
Part VI Finale
16 Conclusion
16.1 Putting it all together
16.2 Impact on Future Work
A Appendix
B Pseudo Codes
C Method to Calculate the Depletion-Region Widths
D Modeling Logical OR Relations.