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Table of Contents
High Level Synthesis
High-Level Synthesis of Digital Circuits from Template Haskell and SDF-AP 1 H. H.
Implementing Synthetic Aperture Radar Backprojection in Chisel A Field Report
EasyHBM: Simple and Fast HBM Access for FPGAs using High-Level Synthesis
Memory Systems
TREAM: A Tool for Evaluating Error Resilience of Tree-based Models using Approximate Memory
SplitnCover: ISO 26262 Hardware Safety Analysis with SystemC
Tagged Geometric History Length Access Interval Prediction for Tightly Coupled Memory Systems
Processor Architecture
NanoController: A Minimal and Flexible Processor Architecture for UltraLow-Power
ControlPULP: A RISC-V Power Controller for HPC Processors with Parallel Control-Law Computation Acceleration
Embedded Software Systems and beyond
CASA: An Approach for exposing and documenting Concurrency-related Software Properties
High-Level Simulation of Embedded Software Vulnerabilities to EM SideChannel Attacks
Deep Learning Optimization I
A Design Space Exploration Methodology for Enabling Tensor Train Decomposition in Edge Devices
Study of DNN-based Ragweed Detection from Drones
PULP-TrainLib: Enabling On-Device Training for RISC-V Multi-Core MCUs through Performance-Driven Autotuning
Extra-functional Property Estimation
The Impact of Dynamic Storage Allocation on CPython Execution Time, Memory Footprint and Energy Consumption: An Empirical Study
Application runtime estimation for AURIX embedded MCU using deep learning
A Hybrid Performance Prediction Approach for Fully-Connected Artificial Neural Networks on Multi-Core Platforms
Deep Learning Optimization I
A Smart HW-Accelerator for Non-Uniform Linear Interpolation of MLActivation Functions
Hardware-Aware Evolutionary Filter Pruning
Innovative Architectures and tools for Security
Obfuscating the Hierarchy of a Digital IP
On the effectiveness of true random number generators implemented on FPGAs
Power and Energy
SIDAM: A Design Space Exploration Framework for Multi-Sensor Embedded Systems Powered by Energy Harvesting
A Data-Driven Approach to Lightweight DVFS-Aware Counter-Based Power Modeling for Heterogeneous Platforms.
High-Level Synthesis of Digital Circuits from Template Haskell and SDF-AP 1 H. H.
Implementing Synthetic Aperture Radar Backprojection in Chisel A Field Report
EasyHBM: Simple and Fast HBM Access for FPGAs using High-Level Synthesis
Memory Systems
TREAM: A Tool for Evaluating Error Resilience of Tree-based Models using Approximate Memory
SplitnCover: ISO 26262 Hardware Safety Analysis with SystemC
Tagged Geometric History Length Access Interval Prediction for Tightly Coupled Memory Systems
Processor Architecture
NanoController: A Minimal and Flexible Processor Architecture for UltraLow-Power
ControlPULP: A RISC-V Power Controller for HPC Processors with Parallel Control-Law Computation Acceleration
Embedded Software Systems and beyond
CASA: An Approach for exposing and documenting Concurrency-related Software Properties
High-Level Simulation of Embedded Software Vulnerabilities to EM SideChannel Attacks
Deep Learning Optimization I
A Design Space Exploration Methodology for Enabling Tensor Train Decomposition in Edge Devices
Study of DNN-based Ragweed Detection from Drones
PULP-TrainLib: Enabling On-Device Training for RISC-V Multi-Core MCUs through Performance-Driven Autotuning
Extra-functional Property Estimation
The Impact of Dynamic Storage Allocation on CPython Execution Time, Memory Footprint and Energy Consumption: An Empirical Study
Application runtime estimation for AURIX embedded MCU using deep learning
A Hybrid Performance Prediction Approach for Fully-Connected Artificial Neural Networks on Multi-Core Platforms
Deep Learning Optimization I
A Smart HW-Accelerator for Non-Uniform Linear Interpolation of MLActivation Functions
Hardware-Aware Evolutionary Filter Pruning
Innovative Architectures and tools for Security
Obfuscating the Hierarchy of a Digital IP
On the effectiveness of true random number generators implemented on FPGAs
Power and Energy
SIDAM: A Design Space Exploration Framework for Multi-Sensor Embedded Systems Powered by Energy Harvesting
A Data-Driven Approach to Lightweight DVFS-Aware Counter-Based Power Modeling for Heterogeneous Platforms.