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Table of Contents
1. Introduction
2. Phase digitization in all-digital PLLs
3. A unifying framework for TDC architectures
4. Analytical predictions of phase noise in ADPLLs
5. Advantages of noise shaping and dither
6. Efficient modeling and simulation of accumulator-based ADPLLs
7. Modelling and estimating phase noise with Matlab.
2. Phase digitization in all-digital PLLs
3. A unifying framework for TDC architectures
4. Analytical predictions of phase noise in ADPLLs
5. Advantages of noise shaping and dither
6. Efficient modeling and simulation of accumulator-based ADPLLs
7. Modelling and estimating phase noise with Matlab.