Low power interconnect design [electronic resource] / Sandeep Saini.
2015
TK7874.53
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Details
Title
Low power interconnect design [electronic resource] / Sandeep Saini.
Author
Saini, Sandeep, author.
ISBN
9781461413233 electronic book
1461413230 electronic book
9781461413226
1461413230 electronic book
9781461413226
Published
New York, NY : Springer, 2015.
Language
English
Description
1 online resource (xvii, 152 pages) : illustrations.
Item Number
10.1007/978-1-4614-1323-3 doi
Call Number
TK7874.53
Dewey Decimal Classification
621.3815
Summary
This book provides practical solutions for delay and power reduction for on-chip interconnects and buses. It provides an in depth description of the problem of signal delay and extra power consumption, possible solutions for delay and glitch removal, while considering the power reduction of the total system. Coverage focuses on use of the Schmitt Trigger as an alternative approach to buffer insertion for delay and power reduction in VLSI interconnects. In the last section of the book, various bus coding techniques are discussed to minimize delay and power in address and data buses. · Provides practical solutions for delay and power reduction for on-chip interconnects and buses; · Focuses on Deep Sub micron technology devices and interconnects; · Offers in depth analysis of delay, including details regarding crosstalk and parasitics; · Describes use of the Schmitt Trigger as a versatile alternative approach to buffer insertion for delay and power reduction in VLSI interconnects; · Provides detailed simulation results to support the theoretical discussions. · Provides details of delay and power efficient bus coding techniques.
Bibliography, etc. Note
Includes bibliographical references.
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Access limited to authorized users.
Source of Description
Online resource; title from PDF title page (SpringerLink, viewed June 15, 2015).
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Table of Contents
Part I Basics of Interconnect Design
Introduction to Interconnects
CMOS Buffer
Part II Buffer and Schmidt trigger Insertion Techniques for Low Power Interconnect Design
Buffer Insertion as a Solution to Interconnect Issues
Schmidt Trigger Approach
Part III Bus Coding Techniques for Low Power Interconnect Design
Bus Coding Techniques.
Introduction to Interconnects
CMOS Buffer
Part II Buffer and Schmidt trigger Insertion Techniques for Low Power Interconnect Design
Buffer Insertion as a Solution to Interconnect Issues
Schmidt Trigger Approach
Part III Bus Coding Techniques for Low Power Interconnect Design
Bus Coding Techniques.