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Can lend chapters, not whole ebooks
Title
Digital logic design using Verilog [electronic resource] : coding and RTL synthesis / Vaibbhav Taraate.
ISBN
9788132227915 (electronic book)
8132227913 (electronic book)
9788132227892
Published
India : Springer, 2016.
Language
English
Description
1 online resource (xix, 402 pages) : illustrations.
Call Number
TK7868.L6
Dewey Decimal Classification
621.39/5
Summary
This book is designed to serve as a hands-on professional reference with additional utility as a textbook for upper undergraduate and some graduate courses in digital logic design. This book is organized in such a way that that it can describe a number of RTL design scenarios, from simple to complex. The book constructs the logic design story from the fundamentals of logic design to advanced RTL design concepts. Keeping in view the importance of miniaturization today, the book gives practical information on the issues with ASIC RTL design and how to overcome these concerns. It clearly explains how to write an efficient RTL code and how to improve design performance. The book also describes advanced RTL design concepts such as low-power design, multiple clock-domain design, and SOC-based design. The practical orientation of the book makes it ideal for training programs for practicing design engineers and for short-term vocational programs. The contents of the book will also make it a useful read for students and hobbyists. .
Bibliography, etc. Note
Includes bibliographical references and index.
Access Note
Access limited to authorized users.
Source of Description
Online resource; title from PDF title page (SpringerLink, viewed May 31, 2016).
Introduction
Combinational Logic Design (Part I)
Combinational Logic Design (Part II)
Combinational Design Guidelines
Sequential Logic Design
Sequential Design Guidelines
Complex Designs using Verilog RTL
Finite State Machines
Simulation Concepts and PLD Based Designs
RTL Synthesis
Static Timing Analysis (STA)
Constraining Design
Multiple Clock Domain Designs
Low Power Design
RTL Design for SOCs.
