Design for testability, debug and reliability : next generation measures using formal techniques / Sebastian Huhn, Rolf Drechsler.
Huhn, Sebastian.; Drechsler, Rolf.
2021
TK7874
Available Online

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Title Design for testability, debug and reliability : next generation measures using formal techniques / Sebastian Huhn, Rolf Drechsler.
Author Huhn, Sebastian.
ISBN 9783030692094 (electronic bk.)
3030692094 (electronic bk.)
9783030692087 (print)
3030692086
DOI https://doi.org/10.1007/978-3-030-69209-4
Imprint Cham : Springer, 2021.
Language English
Description 1 online resource (177 pages)
Other Standard Identifiers 10.1007/978-3-030-69209-4 doi
Call Number TK7874
Dewey Decimal Classification 621.3815
Summary This book introduces several novel approaches to pave the way for the next generation of integrated circuits, which can be successfully and reliably integrated, even in safety-critical applications. The authors describe new measures to address the rising challenges in the field of design for testability, debug, and reliability, as strictly required for state-of-the-art circuit designs. In particular, this book combines formal techniques, such as the Satisfiability (SAT) problem and the Bounded Model Checking (BMC), to address the arising challenges concerning the increase in test data volume, as well as test application time and the required reliability. All methods are discussed in detail and evaluated extensively, while considering industry-relevant benchmark candidates. All measures have been integrated into a common framework, which implements standardized software/hardware interfaces. Provides readers with a combination of a comprehensive set of formal techniques covering and enhancing different aspects of the state-of-the-art design and test flow for ICs; Introduces newly developed heuristic, formal optimization-based and partition-based retargeting techniques and integrates them into a common framework; Describes fully compliant (with respect to industrial de-facto standard) measures to enhance the DFT, DFD and DFR capabilities while supporting standardized data exchange formats; Includes new measures to tackle shortcomings of existing state-of-the-art methods, including zero-defect enforcing safety-critical applications.
Bibliography, etc. Note Includes bibliographical references and index.
Access Note Access limited to authorized users.
Source of Description Description based on print version record.
Online resource; title from PDF title page (SpringerLink, viewed May 4, 2021).
Added Author Drechsler, Rolf.
Available in Other Form Design for Testability, Debug and Reliability.
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Record Appears in Online Resources > Ebooks
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Introduction
Integrated Circuits
Formal Techniques
Embedded Compression Architecture for Test Access Ports
Optimization SAT-based Retargeting for Embedded Compression
Reconfigurable TAP Controllers with Embedded Compression
Embedded Multichannel Test Compression for Low-Pin Count Test
Enhanced Reliability using Formal Techniques
Conclusion and Outlook.

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