Foreword; Preface; Acknowledgments; Contents; Acronyms; 1 Introduction; 1.1 System-Level Design; 1.1.1 Levels of Abstraction; 1.1.2 The Y-Chart; 1.1.3 System-Level Design Methodologies; 1.1.4 Electronic System-Level Design Process; 1.2 Validation and Simulation; 1.2.1 Language Support for System-Level Design; 1.2.2 System Simulation Approaches; 1.2.3 Discrete Event Simulation; 1.3 Goals; 1.4 Overview; 1.5 Related Work; 1.5.1 The SpecC Language; 1.5.2 The SystemC Language; 1.5.3 The System-on-Chip Environment Design Flow; 1.5.4 Multicore Technology and Multithreaded Programming

1.5.5 Efficient Model Validation and Simulation2 The ConcurrenC Model of Computation; 2.1 Motivation; 2.2 Models of Computation; 2.3 ConcurrenC MoC; 2.3.1 Relationship to C-based SLDLs; 2.3.2 ConcurrenC Features; 2.3.3 Communication Channel Library; 2.3.4 Relationship to KPN and SDF; 2.4 Case Study; 3 Synchronous Parallel Discrete Event Simulation; 3.1 Traditional Discrete Event Simulation; 3.2 SLDL Multithreading Semantics; 3.2.1 Cooperative Multithreading in SystemC; 3.2.2 Pre-emptive Multithreading in SpecC; 3.3 Synchronous Parallel Discrete Event Simulation

3.4 Synchronization for Multicore Parallel Simulation3.4.1 Protecting Scheduling Resources; 3.4.2 Protecting Communication; 3.4.3 Channel Locking Scheme ; 3.4.4 Automatic Code Instrumentation for Communication Protection ; 3.5 Implementation Optimization for Multicore Simulation; 3.6 Experiments and Results; 3.6.1 Case Study on a H.264 Video Decoder; 3.6.2 Case Study on a JPEG Encoder ; 4 Out-of-Order Parallel Discrete Event Simulation; 4.1 Motivation; 4.2 Out-of-Order Parallel Discrete Event Simulation; 4.2.1 Notations; 4.2.2 Out-of-Order PDES Scheduling Algorithm

4.3 Out-of-Order PDES Conflict Analysis4.3.1 Thread Segments and Segment Graph; 4.3.2 Static Conflict Analysis; 4.3.3 Dynamic Conflict Detection; 4.4 Experimental Results; 4.4.1 An Abstract Model of a DVD Player; 4.4.2 A JPEG Encoder Model; 4.4.3 A Detailed H.264 Decoder Model; 5 Optimized Out-of-Order Parallel Discrete Event Simulation; 5.1 Optimized Compiler Using Instance Isolation; 5.1.1 Motivation; 5.1.2 Instance Isolation Without Code Duplication; 5.1.3 Definitions for the Optimized Static Conflict Analysis; 5.1.4 Algorithm for Static Conflict Analysis; 5.1.5 Experimental Results

5.2 Optimized Scheduling Using Predictions5.2.1 State Prediction to Avoid False Conflicts; 5.2.2 Static Prediction Analysis; 5.2.3 Out-of-Order PDES Scheduling with Predictions; 5.2.4 Optimized Out-of-Order PDES Scheduling Conflict Checking with a Combined Prediction Table; 5.2.5 Experimental Results; 6 Comparison and Outlook; 6.1 Experimental Setup; 6.1.1 Experimental Environment Setup; 6.1.2 The Parallel Benchmark Models; 6.1.3 The Embedded Applications; 6.2 Parallel Discrete Event Simulation Overlook; 7 Utilizing the Parallel Simulation Infrastructure; 7.1 Introduction