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Table of Contents
Preface; Acknowledgments; Contents; List of Figures; List of Tables; Abbreviations; 1 Introduction; 1.1 Reliability and Electromigration; 1.2 Electromigration in Future Technologies; 1.3 Motivation and Contributions; 1.4 Monograph Outline; 2 State of the Art; 2.1 Mitigating the EM Effects in Different IC Design Flow Stages; 2.1.1 Managing Electromigration in Logic Designs; 2.1.2 Electromigration Impact in Future Technologies; 2.1.3 Smart Non-default Routing for Clock Power Reduction; 2.1.4 Impacts of Electromigration Awareness
2.2 Mitigating the EM Effects in Different Types of Interconnections2.2.1 TSVs; 2.2.2 Power Delivery Network; 2.2.3 Clock Network; 2.2.4 Vias; 2.2.5 Signal Interconnects; 2.2.6 Cell-Internal EM; 2.2.6.1 Accurate Current Estimation for Interconnect Reliability Analysis (Jain12); 2.2.6.2 CMOS Inverter and Standard Cell the Same(patenteempindomae2001cmos); 2.3 Summary of Related Works; 2.4 Conclusions; 3 Modeling Cell-Internal EM; 3.1 Modeling Time-to-Failure Under EM; 3.2 Joule Heating; 3.2.1 Local Hot Spots from Joule Heating; 3.3 Current Divergence
3.3.1 New Electromigration Validation: Via Node Vector Method3.3.2 Applying Current Divergence in the Proposed EM Model; 3.3.3 The Impact of Blech Length on Cell-Internal Interconnects; 3.4 Conclusions; 4 Current Calculation; 4.1 Current Flows Using Graph Traversals; 4.2 Algebra for Average/RMS Current Updates; 4.2.1 Algebra for Computing Average Current; 4.2.2 Algebra for Computing the RMS Current; 4.2.2.1 Example; 4.3 Results; 5 Experimental Setup; 6 Results; 6.1 The Electromigration Effects for Different Logic Gates; 6.1.1 NAND2_X2 and NOR2_X2 Gates
6.1.1.1 TTF Improvement by Layout Modifications6.1.2 AOI21_X2; 6.1.2.1 TTF Improvement by Layout Modifications; 6.1.3 NOR2_X4; 6.1.4 INV_X16; 6.2 Conclusion; 7 Analyzing the Electromigration Effects on Different Metal Layers and Different Wire Lengths; 7.1 Experimental Setup; 7.2 Simulation Results; 7.3 Conclusion; 8 Conclusions; 8.1 Future Works; A Impact on Physical Synthesis Considering Different Amounts of Instances with EM Awareness; B Coupling Capacitance Currents; References
2.2 Mitigating the EM Effects in Different Types of Interconnections2.2.1 TSVs; 2.2.2 Power Delivery Network; 2.2.3 Clock Network; 2.2.4 Vias; 2.2.5 Signal Interconnects; 2.2.6 Cell-Internal EM; 2.2.6.1 Accurate Current Estimation for Interconnect Reliability Analysis (Jain12); 2.2.6.2 CMOS Inverter and Standard Cell the Same(patenteempindomae2001cmos); 2.3 Summary of Related Works; 2.4 Conclusions; 3 Modeling Cell-Internal EM; 3.1 Modeling Time-to-Failure Under EM; 3.2 Joule Heating; 3.2.1 Local Hot Spots from Joule Heating; 3.3 Current Divergence
3.3.1 New Electromigration Validation: Via Node Vector Method3.3.2 Applying Current Divergence in the Proposed EM Model; 3.3.3 The Impact of Blech Length on Cell-Internal Interconnects; 3.4 Conclusions; 4 Current Calculation; 4.1 Current Flows Using Graph Traversals; 4.2 Algebra for Average/RMS Current Updates; 4.2.1 Algebra for Computing Average Current; 4.2.2 Algebra for Computing the RMS Current; 4.2.2.1 Example; 4.3 Results; 5 Experimental Setup; 6 Results; 6.1 The Electromigration Effects for Different Logic Gates; 6.1.1 NAND2_X2 and NOR2_X2 Gates
6.1.1.1 TTF Improvement by Layout Modifications6.1.2 AOI21_X2; 6.1.2.1 TTF Improvement by Layout Modifications; 6.1.3 NOR2_X4; 6.1.4 INV_X16; 6.2 Conclusion; 7 Analyzing the Electromigration Effects on Different Metal Layers and Different Wire Lengths; 7.1 Experimental Setup; 7.2 Simulation Results; 7.3 Conclusion; 8 Conclusions; 8.1 Future Works; A Impact on Physical Synthesis Considering Different Amounts of Instances with EM Awareness; B Coupling Capacitance Currents; References